Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-08-12
2001-08-28
Clark, Jhihan B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S750000, C257S751000, C257S763000, C257S764000
Reexamination Certificate
active
06281584
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of semiconductor chip processing or integrated circuit (IC) fabrication. More particularly, the present invention is related to an interlayer dielectric and the processing steps associated with the interlayer dielectric.
2. Description of the Related Art
Integrated circuits (ICs) often include a number of conductive or metal layers separated by insulative or dielectric layers. The metal layers are generally provided over an insulative layer (ILDO) that covers transistors disposed in a substrate. Each metal layer or stack generally is a composition of several conductive materials, such as, tantalum (Ta), copper (Cu), aluminum (Al), titanium (Ti), tungsten (W), and compounds of copper, tantalum, aluminum, tungsten, nitrogen (N), and titanium. The dielectric layers are generally silicon dioxide (SiO
2
) and are often referred to as interlayer dielectrics or interlevel insulators. The interlayer dielectrics electrically isolate metal layers from each other (e.g., a metal 1 layer from a metal 2 layer).
The interlayer dielectric is typically deposited as silicon dioxide in a chemical vapor deposition (CVD) process. For example, the interlayer dielectric can be provided over a metal layer in a tetraorthosilicate (TEOS) process. After the interlayer dielectric is planarized, a metal layer is provided over the interlayer dielectric.
Generally, it is desirable to reduce the capacitance associated with the metal layers in an IC. Reducing capacitance increases the speed of the IC and is a particularly important design goal as IC devices become smaller. One technique for reducing the capacitance associated with the metal layers is to reduce the dielectric constant associated with the interlayer dielectric (e.g., the insulating layer between metal layers).
Fluorinated silicon dioxide (SiOF) material can be used as the interlayer dielectric instead of silicon dioxide material to lower the capacitance associated with the metal layers. Fluorinated silicon dioxide has a lower dielectric constant than silicon dioxide. For example, fluorinated silicon dioxide has a dielectric constant in a range from 3.6 to 3.8, while silicon dioxide has a dielectric constant of 4.0 or more. Fluorinated silicon dioxide is typically provided by plasma enhanced chemical vapor deposition (PECVD) or a high density plasma (HDP) application technique. Therefore, utilizing fluorinated silicon dioxide can reduce the capacitance associated with the semiconductor device and thereby increase its speed and performance.
Fluorine atoms in fluorinated silicon dioxide can react with barrier metals (Ti, TiN, Ta, TaN, Al, Cu, etc) associated with the metal layers. The barrier metals are typically deposited (BMD) by plasma vapor deposition (PVD) or chemical vapor deposition (CVD) on the surface of the fluorinated silicon dioxide. For example, in an IC containing two metal layers, a barrier metal for the second metal layer is deposited on the interlayer dielectric which covers the first metal layer. The barrier metal layer is typically located on the bottom of the composite metal layer. The reaction between the fluorine and the barrier metal can cause delamination and other adhesion problems.
In addition, the reaction can cause delamination and adhesion problems inside vias (e.g., holes) which extend through the fluorinated silicon dioxide. Contacts or electrical connections between metal layers are made through vias in the interlayer dielectric. Delamination and adhesion problems can also exist at the interface between the titanium nitride layer and the fluorinated silicon dioxide layer. The titanium and titanium nitride layers are typically located at the top of the composite metal layers.
Thus, there is a need for an IC which is less susceptible to adhesion and delamination problems. Further still, there is a need for a method of manufacturing an IC that reduces adhesion and delamination problems associated with fluorinated silicon dioxide.
SUMMARY OF THE INVENTION
The present invention relates generally to an integrated circuit including a first metal stack, a second metal stack, and a fluorinated silicon dioxide material. The fluorinated silicon dioxide material is disposed between the first metal stack and second metal stack. The material has a surface that is depleted by a process that utilizes ammonia and is passivated in a process that utilizes nitrite.
The present invention further relates to an integrated circuit including a first conductive layer, a second conductive layer, and an insulative layer. The insulative layer includes fluorinated silicon dioxide. The insulative layer has a surface in contact with the second conductive layer. The surface is depleted of fluorine to a first depth and is passivated to a second depth. The second depth is less than the first depth. The surface is depleted by a process including ammonia, or the surface is passivated in a process including nitrite.
The present invention also relates generally to a method for fabricating an integrated circuit. The integrated circuit includes a first metal stack, a dielectric layer, and a second metal stack. The dielectric layer is between the first metal stack and the second metal stack. The method includes steps of providing the first metal stack, providing the dielectric layer as a layer of SiOF, depleting the fluorine from a surface of the layer of SiOF with a plasma including NH
3
, and providing the second metal layer.
The present invention further relates to a method for using low dielectric constant SiOF in a process to manufacture semiconductor integrated circuits. The method includes steps of obtaining a layer of SiOF and treating the surface of the layer of SiOF with a plasma containing ammonia to deplete fluorine from the surface.
The present invention further still relates to a semiconductor chip. The semiconductor chip includes an integrated circuit with at least a first layer and a second layer. A dielectric layer of SiOF is disposed between the first layer and the second layer. The dielectric layer has a surface depleted of fluorine to a depth. The dielectric layer is depleted in an ammonia process.
The present invention even further relates to a method of forming metal layers in an integrated circuit. The method includes providing a first metal stack, providing a dielectric layer including fluorine, depleting the fluorine from an exposed surface of the dielectric layer with an ammonia treatment, and providing a second metal stack over the dielectric layer.
REFERENCES:
patent: 5872402 (1999-02-01), Hasegawa
patent: 5946601 (1999-08-01), Wong et al.
patent: 5989983 (1999-11-01), Goo et al.
patent: 6043145 (2000-03-01), Suzuki et al.
patent: 8-203890 (1996-08-01), None
patent: 10-275859 (1998-10-01), None
patent: 11-40669 (1999-02-01), None
Huang Richard J.
Morales Guarionex
Ngo Minh Van
Advanced Micro Devices , Inc.
Clark Jhihan B
Foley & Lardner
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