Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
1999-04-21
2001-04-10
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S686000
Reexamination Certificate
active
06215193
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to multichip modules (MCM) and a manufacturing method therefor, and more particularly to multichip modules and a manufacturing method in which a recess is provided in a substrate during manufacturing of the substrate of a ball grid array integrated circuit for receiving an integrated circuit or memory stack.
2. Description of the Related Art
In order to reduce the volume of an electric device, integrated circuits are packaged in stacks to form a multichip module to reduce the surface area of the substrate occupied by the electric device.
U.S. Pat. No. 5,323,060 to Fogal et al. issued on Jun. 21, 1994 discloses a multichip module having a stacked chip arrangement. In this patent, as shown in
FIG. 1
of the drawings that corresponds to
FIG. 1
of U.S. Pat. No. 5,323,060, the multichip includes a substrate
100
, a first multichip stack
110
, and a second multichip stack
120
. The first multichip stack
110
includes a first chip
112
mounted to a bonding area
111
of the substrate
100
. An adhesive layer
113
is applied to upper face of the first chip
112
. A second chip
114
is then mounted on top of the adhesive layer
113
, thereby forming a multichip stack with two chips. A number of bonding wires
115
interconnect bonding pads of the chips
112
and
114
and bonding pads of the substrate
100
. The adhesive layer
113
must have a thickness of “A” to allow connection between the bonding wires
115
and the bonding pads of the chips
112
and
114
. The second multichip stack
120
includes a first chip
122
mounted to a bonding area
121
of the substrate
100
. A first adhesive layer
123
is applied to upper face of the first chip
121
. A second chip
124
is mounted on top of the first adhesive layer
123
, and a second adhesive layer
125
is then applied to upper face of the second chip
124
. Next, a third chip
126
is mounted on top of the second adhesive layer
125
, and a third adhesive layer
127
is applied to upper face of the third chip
126
for mounting a further chip, thereby forming a multichip stack with many chips. A number of bonding wires
128
interconnect bonding pads of the chips
122
,
124
, and
126
and bonding pads of the substrate
100
. The adhesive layers
123
,
125
, and
127
must have a thickness of “A” to allow connection between the bonding wires
128
and the bonding pads of the chips
122
,
124
, and
126
. Nevertheless, the adhesive layers
113
,
123
,
125
, and
127
must have a thickness of “A” to prevent the chips
114
,
124
, or
126
from making contact with the underlying bonding wires
115
or
128
. Yet the increase in the thickness of the adhesive layers
113
,
123
,
125
, and
127
results an obstacle to heat transfer from the chips
114
,
124
, and
126
to the underlying chips. The heat dissipating effect is accordingly poor.
U.S. Pat. No. 5,804,004 to Tuckerman et al. issued on Sep. 8, 1998 discloses stacked devices for multichip modules. In this patent, as shown in
FIGS. 2 and 3
of the drawings that correspond to
FIGS. 4A and 4B
of U.S. Pat. No. 5,804,004, the multichip includes a substrate
200
, and a first chip
211
is mounted to upper face of the substrate
200
by an adhesive layer ai
210
. Bonding pads
215
of the first chip
211
are connected to bonding pads
201
of the substrate
200
by bonding wires
214
. A second chip
212
is mounted to upper face of the first chip
211
by an adhesive layer
210
. Bonding pads
215
of the second chip
212
are connected to bonding pads
202
of the substrate
200
by bonding wires
214
. Bonding wires
214
are prevented from making contact with the adjacent upper chip
212
by beveling the edge of the upper second chip
212
. A third chip
213
is mounted to upper face of the second chip
212
by an adhesive layer
210
. Bonding pads
215
of the third chip
213
are connected to bonding pads
203
of the substrate
200
by bonding wires
214
. Bonding wires
214
are prevented from making contact with the adjacent upper chip
213
by beveling the edge of the upper third chip
213
. Nevertheless, beveling of the edge of the chip
212
,
213
results in difficulty in manufacturing.
SUMMARY OF THE INVENTION
It is a primary object of the present invention to provide a multichip module that includes a substrate having two padding strips to allow a chip or an electric device to be mounted between the padding strips in a manner that the upper face does not extend beyond the padding strips. The padding strips provide a cushioning effect for the chip or electric device during wire bonding procedure of the chip or electric device.
It is a secondary object of the present invention to provide a multichip module that includes a substrate having a recess for receiving a chip or electric device such that the chip or electric device is “sunk” into the substrate in a manner that the upper face does not extend beyond the substrate. Another chip or electric device is mounted above this chip or electric device, yet the overall height of the multichip module thus formed is reduced.
It is a further object of the present invention to provide a method for manufacturing a multichip module, wherein bonding pads of a lower chip are exposed outside lateral edges of an upper chip to allow easy wire bonding and to avoid the bonding wires from making contact with the upper chip. In addition, the thickness of the adhesive layers between the upper chip and the lower chip is reduced to allow easy heat conduction from the upper chip to the lower chip and to avoid flush of adhesive from an area between the upper chip and the lower chip to an area beyond the upper chip and the lower chip.
In accordance with the present invention, a substrate includes two padding strips, a first chip, and a second chip. The padding strips are mounted on both sides of the first chip. An adhesive layer is applied to a lower face of the first chip so as to be adhered to the substrate. A further adhesive layer is applied to an upper face of the first chip for adherence with a lower face of the second chip. Bonding pads on two ends of the first chip between the padding strips extend beyond the lateral edges of the second chip rather than being covered by the second chip. Wire bonding of bonding pads on two ends of the first chip is convenient as not being affected by the second chip. In addition, the padding strips provide a cushioning effect when the first chip is subjected to forces during wire bonding of the second chip, thereby making the first chip more reliable.
In another preferred embodiment of the invention, the substrate includes a single padding strip for stacking the second chip above the first chip. Bonding pads on two ends of the first chip extend beyond the lateral edges of the second chip rather than being covered by the second chip. Wire bonding of bonding pads on two ends of the first chip is convenient as not being affected by the second chip. In addition, the padding strip provides a cushioning effect when the first chip is subjected to forces during wire bonding of the second chip, thereby making the first chip more reliable.
In a further preferred embodiment of the invention, the substrate includes a recess for receiving a first chip, and a second chip is stacked above the first chip. Provision of the recess reduces the overall height of the multichip module of the invention and shortens the length of the bonding wires for connecting the bonding pads of the first chip and the bonding pads of the substrate. Two side adhesive layers are applied to both sides of the recess for stacking the second chip in a manner that bonding pads on two ends of the first chip extend beyond the lateral edges of the second chip rather than being covered by the second chip. Wire bonding of bonding pads on two ends of the first chip is convenient as not being affected by the second chip. In addition, both sides of the recess provide a cushioning effect when the first chip is subjected to forces during wire bonding o
Lin Meng-Hui
Tao Su
Advanced Semiconductor Engineering Inc.
Clark Sheila V.
Dykema Gossett PLLC
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