Self-aligned extension junction for reduced gate channel

Details Self-aligned extension junction for reduced gate channel Self-aligned extension junction for reduced gate channel

2000-06-02

2001-03-20

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S182000, C438S300000, C438S303000, C438S542000, C438S589000, C438S595000

Reexamination Certificate

active

06204133

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the manufacture of high performance semiconductor integrated circuit devices. More specifically, this invention relates to the manufacture of high performance semiconductor transistors having reduced channel lengths. Even more specifically, this invention relates to the manufacture of high performance semiconductor transistors having reduced channel lengths and self-aligned lightly doped drain (LDD) extensions.
2. Discussion of the Related Art
Several performance enhancers for modern semiconductor devices are critical as high performance transistors are scaled to further enhance performance. For example, as the channel length of the transistor is reduced, features such as the lightly doped-drain (LDD) extension regions have been added to solve some of the problems associated with short-channel effects that have resulted from the shortened channel length.
A major obstacle to the formation of very short channel devices is the limitation of commercially available sources of illumination for use in manufacturing processes. The non-availability of illumination devices that would allow the printing of very small features on a layer of photoresist that are then transferred to a further layer, such as a layer of polysilicon. For a “classic” gate structure, the photoresist pattern is first reduced by a well-known resist trimming technique. However, this reduction also reduces the amount of polysilicon, thus increasing the resistance of the device. To then remedy this problem, thicker layers of polysilicon are deposited. However, thicker polysilicon increases the aspect ratio between two adjacent features that results in a non-uniform etch. Another problem of the classic gate manufacturing method is that the upper surface “landing pad” is too small for the next layer, such as an interconnect layer, to properly align upon. The remedy the small upper landing surface, “T” or “notched” gates have been attempted. However, these irregular shaped features require angular or lateral implants to form LDD under the notches. These angular or lateral implants produce poor implant profiles and the resultant overlapping capacitances are not optimal.
Therefore, what is needed is a method to utilize currently commercially available illumination sources, materials, and equipment in such a way that well understood processes can continue to be used to manufacture high performance semiconductor devices.
SUMMARY OF THE INVENTION
According to the present invention, the foregoing and other objects and advantages are attained by a method of manufacturing a semiconductor device having a self-aligned extension junctions and a reduced gate channel length.
In accordance with an aspect of the invention, a layer of phosphoro silicate glass is formed on a substrate. A layer of photoresist is formed on the layer of phosphoro silicate glass, patterned and developed to expose a portion of the phosphoro silicate glass. The phosphoro silicate glass is etched to form an opening to the underlying substrate. Spacers are formed on the walls of the opening. A thermal process forms the LDD extensions by diffusing ions from the phosphoro silicate glass, which serves as a self-aligned solid diffusions source. A gate structure is formed and S/D junctions are formed.
In another aspect of the invention, the gate structure is formed by forming a photoresist gate mask on a blanket layer of polysilicon and etching the polysilicon and underlying layer of phosphoro silicate glass.
In another aspect of the invention, the gate structure is formed by a blanket anisotropic etch to remove the excess portions of the layer of polysilicon.
In another aspect of the invention, the gate structure is formed by chemically mechanically polishing the excess portions of the layer of polysilicon.
The method of the present invention thus effectively provides a semiconductor manufacturing process that uses a patterned layer of phosphoro silicate glass as a self-aligning solid diffusion source to form LDD extensions and a reduced gate channel length.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described embodiments of this invention simply by way of illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications in various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.


REFERENCES:
patent: 5545579 (1996-08-01), Liang et al.
patent: 5766998 (1998-06-01), Tseng
patent: 6087208 (2000-07-01), Krivokapic et al.
patent: 6090691 (2000-07-01), Ang et al.

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