Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Utility Patent
1998-10-28
2001-01-02
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S396000, C438S399000
Utility Patent
active
06168992
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of microelectronics and more particularly to methods of forming electrodes for microelectronic devices.
BACKGROUND
With continued increases in integration densities of Dynamic Random Access Memory (DRAM) devices, steps used to fabricate DRAM memory cell capacitors with high capacitances are becoming more complicated and difficult. In addition, alignment between the storage electrode contact hole and the storage electrode is more difficult to provide. In other words, while a diameter of the storage electrode contact hole is reduced to occupy a smaller area, a surface area of the capacitor is desirably increased to provide a high capacitance.
In particular, methods have been developed to form Hemi-Spherical Grain (HSG) silicon layers on storage electrodes to increase surface areas thereof. With HSG silicon layers, however, it may be necessary that extra space be provided between storage electrodes so that bridging does not occur between electrodes when forming the HSG layer. Otherwise, bridging between electrodes may result in double-bit and multi-bit failures.
An overlap margin between a storage electrode contact hole and a storage electrode may thus be reduced so that a polysilicon layer formed in a storage electrode contact hole is etched during storage electrode poly-etching. If the degree of etching is serious, the polysilicon in the contact hole may be severely etched, and an undesirably high resistance between the capacitor storage electrode and the memory cell access transistor may result.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved methods of fabricating microelectronic electrodes.
It is another object of the present invention to provide improved methods of fabricating microelectronic capacitor structures.
It is still another object of the present invention to provide improved methods of fabricating dynamic random access memory devices.
These and other objects are provided according to the present invention by forming a sacrificial layer on a substrate, forming a contact hole through the sacrificial layer, and forming a conductive plug in the contact hole. The sacrificial layer is then removed thereby exposing upper side portions of the conductive plug and defining an electrode. An electrode with sidewalls is thus provided thereby increasing the surface area of the electrode. More particularly, the step of forming the sacrificial layer can be preceded by the steps of forming an insulating layer on the substrate, and forming an etch stop layer on the insulating layer wherein the contact hole is formed through the sacrificial layer, the etch stop layer, and the insulating layer. The electrode and the conductive via are thus provided simultaneously with improved alignment therebetween. In other words, the portion of the conductive plug in the insulating layer provides the conductive via, and the portion of the conductive plug in the sacrificial layer provides the electrode.
According to a particular embodiment of the present invention, methods are provided for fabricating a Dynamic Random Access Memory (DRAM) device. These methods include the steps of forming a word line on a substrate, forming a first insulating layer on the substrate and on the word line, forming a bit line on the first insulating layer, and forming a second insulating layer on the first insulating layer and on the bit line. A sacrificial layer is formed on the second insulating layer, and a contact hole is formed through the sacrificial layer, and the first and second insulating layers. A conductive plug is formed in the contact hole, and the sacrificial layer is removed thereby exposing upper side portions of the conductive plug to define a capacitor electrode. In addition, a dielectric layer can be formed on the exposed portions of the conductive plug, and a conductive layer can be formed on the dielectric layer opposite the conductive plug to provide a capacitor structure.
More particularly, the step of forming the sacrificial layer can be preceded by the step of forming an etch stop layer on the second insulating layer opposite the substrate, and the step of forming the contact hole can include forming the contact hole through the etch stop layer. The etch stop layer can be a layer of a material that generates a polymer during the step of forming the contact hole so that a width of the contact hole through the sacrificial layer can be greater than a width of the contact hole through the first and second insulating layers. For example, the etch stop layer can be a layer of a material such as polycrystalline silicon or silicon nitride. The etch stop layer can be removed after removing the sacrificial layer, and the etch stop layer can have a thickness in the range of 500 Ångstroms to 1500 Ångstroms. The sacrificial layer can have a thickness in the range of 8,000 Ångstroms to 12,000 Ångstroms.
According to the methods of the present invention, a conductive plug can be formed in a contact hole through a sacrificial layer and an insulating layer, and the sacrificial layer can be removed to simultaneously provide both an electrode and a conductive via. Because a single photolithography step can be used to define the contact hole through both the sacrificial and insulating layers, alignment of the electrode and the conductive via can be improved.
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Fourson George
Garcia Joannie A.
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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