Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-12-10
2001-03-27
Zarabian, Amir (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S238000, C438S275000, 43, C257S306000, C257S314000
Reexamination Certificate
active
06207490
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same, and in particular, to a semiconductor device and a fabricating method thereof, which can maximize a cell integration level.
2. Description of the Related Art
Along with higher integration of semiconductor devices, reduction of pattern pitch, that is, circuit line width has become a significant interest in a semiconductor fabrication process. The decrease in the circuit line width plays an important role in shrinkage of semiconductor devices and is achieved by development of photolithography. That is, the circuit line width has been reduced by improving many parameters including the resolution of a photoresist used, the range of an optical wavelength used, and so on. For example, a 436-nm g-line was initially used but now a 365-nm i-line is currently used, for photolithography. In addition, a 248-nm KrF excimer laser will be used in the future. The resolution of a photoresist increases with the reduction of an optical wavelength and the increase in the aperture of an exposure equipment, and thus high integration and high capacity can be realized.
FIGS. 1A and 1B
are sectional views sequentially illustrating a conventional semiconductor fabricating method disclosed in U.S. Pat. No. 4,430,791.
Referring to
FIG. 1A
, an active region and a field region are defined in a P
−
semiconductor substrate
10
by forming a field oxide film
12
by a general device isolation process. Here, a channel stop layer
14
may be formed under the field oxide film
12
to enhance device isolation characteristics.
Subsequently, a gate oxide film
16
is grown on the active region of the substrate
10
by oxidation, and then a first polysilicon layer
20
, a nitride (Si
3
N
4
) film
22
, and a second polysilicon layer
24
are sequentially formed on the gate oxide film
16
.
Referring to
FIG. 1B
, the second polysilicon layer
24
is patterned by photolithography. Here, the nitride film
22
acts as an etch stop layer. Then, an insulating film is deposited on the resultant structure and etched back to form insulating film spacers
26
on the sidewalls of the patterned second polysilicon layer
24
.
Then, after the second polysilicon layer
24
is removed, a gate electrode is formed by etching the underlying nitride film
22
and the first polysilicon layer
20
, using the insulating film spacers
26
as an etching mask.
FIGS. 2A
,
2
B, and
2
C are sectional views sequentially illustrating another conventional semiconductor device fabricating method disclosed in U.S. Pat. No. 4,649,638.
Referring to
FIG. 2A
, a pad oxide film (not shown) and a nitride film
30
are sequentially formed on a P-type semiconductor substrate
28
, and an active region is defined by patterning the nitride film
30
by photolithography. Then, a field oxide film
34
is formed by thermal oxidation, using the patterned nitride film
30
as an oxidation blocking mask. During the oxidation, oxygen penetrates into a lateral surface of the pad oxide film (not shown) from under the nitride film
30
used as a mask, thereby producing a bird's beak
36
at an edge of the field oxide film
34
.
Referring to
FIG. 2B
, the underlying field oxide film
34
is anisotropically etched by self-alignment etching, in which the nitride film
30
having the bird's beak
36
thereunder is used as an etching mask. As a result, an abutment
24
having a vertical wall
40
is produced. Then, the nitride film
30
and the pad oxide film (not shown) are removed. Here, reference numeral
42
denotes a slanted roof of the abutment
24
.
Referring to
FIG. 2C
, a gate oxide film
44
is formed by performing an oxidation process on the resultant structure, and then a conductive layer for a gate electrode is deposited, on the gate oxide film
44
. Then, a gate electrode
16
is formed on the sidewall of the abutment
24
, in the form of a spacer by anisotropically etching the conductive layer.
Then, an N
+
source/drain region (not shown) is formed by ion-implanting an N-type impurity, using the gate electrode
16
as an ion-implanting mask. At this time, a lightly doped drain (LDD) structure of a single channel is automatically formed without an additional step by ion-implantation in self-alignment with the slanted roof and the slope of the gate electrode
44
.
According to the above-described conventional methods, a transistor can be formed to have a channel length equal to the width of a spacer. However, the spacer width, especially a smaller spacer width, varies to a large extent in a wafer or from wafer to wafer. Therefore, uniformity and reproductability of the channel length in the transistor cannot be ensured.
Causes of varying the spacer width will be described hereinbelow.
(1) A spacer film is non-uniformly deposited according to wafer location, chip location, ad adjacent patterns due to a gas flow and the aspect ratio of an adjacent pattern. Hence, the thickness of the spacer deposited determines its width, making the width non-uniform. For example, when a spacer film is deposited on an active region and a field region as shown in
FIG. 1A
, a reaction gas is applied to a substrate at different rates by CVD (Chemical Vapour Deposition), resulting in different spacer widths in both regions having different aspect ratios.
(2) Even though the spacer film is uniformly deposited, there is a difference between the etch rates of the center and an edge of a wafer during an etch-back step due to characteristics unique to anisotropical etching. Generally, the etch rate at the center of the wafer is higher than that at the edge thereof. Therefore, the spacer width at the center of the wafer is the smallest.
In addition, use of the spacer width to determine the most sensitive characteristics of a device such as the channel length of a transistor becomes a large obstacle to chip shrinkage, in the conventional methods. That is, a possibly obtained small channel length gives no benefit unless a punchthrough margin is obtained. Further, even though the punchthrough margin can be obtained, non-uniformity of device characteristics caused by short channel effects worsens the non-uniformity caused by variation of the spacer width.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a semiconductor device which employs a cell structure for which use of a spacer mask generates no serious uniformity problem to thereby contribute to maximization of cell integration.
Another object of the present invention is to provide a suitable method of fabricating the above semiconductor device.
To achieve one object of the present invention, there is provided a semiconductor device. In the semiconductor devices, a plurality of buried diffusion layers repeatedly extend on a semiconductor substrate. A plurality of word lines repeatedly extend over the buried diffusion layers, perpendicularly thereto, and have asymmetrical polygonal cross-sections, with odd-numbered word lines having the same cross-section and even-numbered word lines having the same cross-section.
It is preferred that the odd-numbered word lines have a mirror symmetry with respect to the even-numbered word lines.
According to another aspect of the present invention, there is provided a semiconductor device. In the semiconductor device having a memory cell array region and a peripheral circuit region for driving a cell, a plurality of buried diffusion layers repeatedly extend on a semiconductor substrate, as bit lines and sources/drains of cell transistors in the memory cell array region. A plurality of word lines repeatedly extend as gate electrodes of the cell transistors on the substrate having the buried diffusion layer formed thereon in the memory cell array region, perpendicularly to the buried diffusion layers. Here, the gate electrodes of the cell transistors in the memory cell array region have asymmetrical polygonal cross-sections, and the deposition structure on the gate electrodes of the cell tran
Luu Pho
Marger Johnson & McCollom PC
Samsung Electronics Co,. Ltd.
Zarabian Amir
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