MOS Transistor formation process including post-spacer etch...

Details MOS Transistor formation process including post-spacer etch... MOS Transistor formation process including post-spacer etch...

1999-07-27

2001-01-09

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S586000, C438S655000

Reexamination Certificate

active

06171919

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of manufacturing high-density integrated circuit semiconductor devices exhibiting reliable, adherent, low resistance, well-aligned contacts to source, drain, and gate electrode regions of active devices, such as MOS transistors formed in or on a semiconductor substrate, by utilizing self-aligned, refractory metal suicide (“salicide”) processing methodology. The present invention has particular utility in manufacturing high-density integration semiconductor devices, including multi-level devices, with design rules of 0.18 &mgr;m and below, e.g., 0.15 &mgr;m and below.
BACKGROUND OF THE INVENTION
The escalating requirements for high density and performance associated with ultra-large scale integration (ULSI) devices necessitate design rules of 0.18 &mgr;m and below, such as 0.15 &mgr;m and below, with increased transistor and circuit speeds, high reliability, and increased manufacturing throughput. The reduction of design features, e.g., of source, drain, and gate regions of transistors formed in or on a common semiconductor substrate, challenges the limitations of conventional contact and interconnection technology, including conventional photolithographic, etching, and deposition techniques.
As a result of the ever-increasing demand for large-scale and ultra-small dimensioned integrated semiconductor devices, self-aligned techniques have become the preferred technology for forming such devices in view of their simplicity and capability of high-density integration. As device dimensions decrease in the deep sub-micron range, both vertically and laterally, many problems arise, especially those caused by an increase in sheet resistance of the contact areas to the source and drain regions and junction leakage as junction layer thickness decreases. To overcome this problem, the use of self-aligned, highly electrically conductive refractory metal suicides, i.e., salicides, has become commonplace in the manufacture of integrated circuit semiconductor devices comprising, e.g., MOS type transistors. Another technique employed in conjunction with refractory metal silicide technology is the use of lightly-doped source and drain extensions formed just at the edge of the gate region, while more heavily-doped source and drain regions, to which ohmic contact is to be provided, are laterally displaced away from the gate by provision of sidewall spacers on opposing sides of the gate electrode.
Salicide processing involves deposition of a metal that forms an intermetallic compound with silicon, but does not react with silicon oxides, nitrides, or oxynitrides under normal processing conditions. Refractory metals commonly employed in salicide processing include platinum (Pt), titanium (Ti), nickel (Ni), and cobalt (Co), each of which forms very low resistivity phases with silicon (Si), e.g., PtSi
2
, TiSi
2
, NiSi, and CoSi
2
. In practice, the refractory metal is deposited in uniform thickness over all exposed upper surface features of a Si wafer, preferably by means of physical vapor deposition (PVD) from an ultra-pure sputtering target and an ultra-high vacuum, multi-chamber DC magnetron sputtering system. In MOS transistor formation, deposition is generally performed after gate etch and source/drain junction formation. In a less common variant, source/drain junction formation is effected subsequent to refractory metal layer deposition via dopant diffusion through the refractory metal layer into the underlying semiconductor. In either case, after deposition, the refractory metal layer blankets the top surface of the gate electrode, typically formed of heavily-doped polysilicon, the silicon oxide, nitride, or oxynitride sidewall spacers on the opposing side surfaces of the gate electrode, the silicon oxide isolation regions formed in the silicon substrate between adjacent active device regions, and the exposed surfaces of the substrate where the source and drain regions are formed or will be subsequently formed. As a result of thermal processing, e.g., a rapid thermal annealing process (RTA) performed in an inert atmosphere, the refractory metal reacts with underlying Si to form electrically conductive silicide layer portions on the top surface of the polysilicon gate electrode and on the exposed surfaces of the substrate where source and drain regions are or will be formed. Unreacted portions of the refractory metal layer, e.g., on the silicon oxide, nitride, or oxynitride sidewall spacers and the silicon oxide isolation regions, are then removed, as by a wet etching process selective to the metal silicide portions. In some instances, e.g., with Co, a first RTA step may be performed at a relatively lower temperature in order to form first-phase CoSi which is then subjected to a second RTA step performed at a relatively high temperature to convert the first-phase CoSi to second-phase, lower resistivity CoSi
2
.
Illustrated in FIGS.
1
(A)-
1
(E) are steps in a typical salicide process, illustratively CoSi
2
, for manufacturing MOS transistors and CMOS devices according to one process scheme of the conventional art. The term “semiconductor substrate” as employed throughout the present disclosure and claims, denotes a Si-containing wafer, e.g., a monocrystalline Si wafer, or an epitaxial Si-containing layer formed on a semiconductor substrate and comprising at least one region
1
of a first conductivity type. It will be appreciated that for P-MOS transistors, region
1
is n-type and for N-MOS transistors, region
1
is p-type. It is further understood that the substrate may comprise pluralities of n- and p-type regions arrayed in a desired pattern, as, for example, in CMOS devices.
Referring more particularly to FIG.
1
(A), reference numeral
1
indicates a region or portion of a Si-containing semiconductor substrate of a first conductivity type (p or n), fabricated as a MOS transistor precursor
2
for use in a salicide process scheme. Precursor
2
is processed, as by conventional techniques not described here in detail, in order to not unnecessarily obscure the primary significance of the following description. Precursor
2
comprises a plurality of, illustratively two, isolation regions
3
and
3
′ of a silicon oxide, e.g., shallow trench isolation (STI) regions, extending from the substrate surface
4
to a prescribed depth below the surface. A gate insulator layer
5
, typically comprising a silicon oxide layer about 25-50 Å thick, is formed on substrate surface
4
. Gate electrode
6
, typically of heavily-doped polysilicon, is formed over a portion of silicon oxide gate insulator layer
5
, and comprises opposing side surfaces
6
′,
6
′, and top surface
6
″. Blanket layer
7
of an insulative material, typically an oxide, nitride, or oxynitride of silicon, is then formed to cover all exposed portions of substrate surface
4
and the exposed surfaces of the various features formed thereon or therein, inter alia, the opposing side surfaces
6
′,
6
′ and top surface
6
″ of gate electrode
6
and the upper surface of STI regions
3
,
3
′. The thickness of blanket insulative layer
7
is selected so as to provide sidewall spacers
7
′,
7
′ of desired width (see below) on each of the opposing side surfaces
6
′,
6
′ of the gate electrode
6
.
Referring now to FIG.
1
(B), MOS precursor structure
2
is then subjected to an anisotropic etching process, as by reactive plasma etching utilizing a fluorocarbon- or fluorohydrocarbon-based plasma comprising argon (Ar) and at least one reactive gaseous species selected from CF
4
and CHF
3
, for selectively removing the laterally extending portions of insulative layer
7
and underlying portions of the gate oxide layer
5
, whereby sidewall spacers
7
′,
7
′ of desired width profile are formed along the opposing side surfaces
6
′,
6
′ of gate electrode
6
.
Adverting to FIG.
1
(C), moderately- to heavily-doped source and drain junction regions
8
and
9
of conductivity ty

Affiliated with

Also associated with

Rating

MOS Transistor formation process including post-spacer etch... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with MOS Transistor formation process including post-spacer etch..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MOS Transistor formation process including post-spacer etch... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2477928