Method for forming split gate non-volatile memory cells...

Details Method for forming split gate non-volatile memory cells... Method for forming split gate non-volatile memory cells...

1998-12-16

2001-05-08

Nelms, David (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S261000, 43

Reexamination Certificate

active

06228723

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for forming a split gate non-volatile memory cell on a semiconductor substrate, and more particularly to a method for forming a split gate non-volatile memory cell without forming a conductive layer on a boundary region between a memory cell array and peripheral logic in a semiconductor substrate.
BACKGROUND OF THE INVENTION
Non-volatile memory devices, including erasable programmable read only memory (EPROM) and electrically erasable programmable read only memory (EEPROM), have the capability of maintaining stored information after the power supply is removed. One type of EPROM includes a single transistor cell having a control gate and a floating gate, the floating gate being between the control gate and a silicon substrate. An EEPROM cell generally employs two transistors.
The conventional method of forming a split gate non-volatile memory cell in a semiconductor device is depicted in
FIGS. 1A
to
1
D. Referring to
FIG. 1A
, a semiconductor substrate
10
has a cell array region a, a boundary region b, and a peripheral logic region (not shown). A field oxide layer
12
is formed in and on semiconductor substrate
10
. A gate oxide layer
13
is formed over an active region of the cell array region a. To manufacture a floating gate of a transistor, a first conductive or polysilicon layer
14
is formed on the field oxide layer
12
and the gate oxide layer
13
. An interpoly oxide layer
16
is disposed on the first polysilicon layer
14
. The first polysilicon layer
14
and the interpoly oxide layer
16
are patterned to produce a terminal edge
15
, which is over the boundary region b. For control gates of memory cells and gates of transistors in the peripheral logic region, a second conductive or polysilicon layer
18
is formed over the semiconductor substrate
10
. A self aligned etching mask
20
, e.g., a photoresist pattern, is deposited on selected portions of the second polysilicon layer
18
. Referring to
FIG. 1B
, portions of the first and second polysilicon layers
14
and
18
and the interpoly oxide layer
16
, which are not protected by the mask
20
, are removed to produce a split gate
22
. The split gate
22
includes a control gate
18
a
and a floating gate
14
a
, separated by a remaining portion
16
a
of the interpoly oxide layer. Thereafter, the mask
20
is removed. The remaining structure additionally includes conductive layers
18
b
and
14
b
, and an interpoly oxide layer
16
b
overlying boundary region b.
Referring to
FIG. 1C
, a second mask or photoresist layer
24
is selectively formed on the resulting structure of FIG.
1
B. The photoresist layer
24
does not cover a selected portion
19
of the conductive layer
18
b
. The exposed portion
19
of the second conductive layer
18
is then etched to form the gates (not shown) of transistors in the peripheral logic region.
The second photoresist layer
24
is removed to produce the structure illustrated in FIG.
1
D. As shown in
FIG. 1D
, an electrically conductive structure
26
, which includes the conductive layers
14
b
and
18
b
and interpoly oxide layer
16
b
, overlies boundary region b. The conductive structure
26
can cause a local charge-up phenomenon during the photolithography process. The charge-up can produce an arc or electrical discharge that causes structural damage or creates polysilicon particle contamination. Accordingly, a process is desired which eliminates the formation of a conductive layer overlying the boundary region b.
SUMMARY OF THE INVENTION
The present invention is intended to solve the aforementioned problems by providing a method for forming split gate non-volatile memory cells without leaving a conductive layer overlying a boundary region of a semiconductor substrate.
The method includes forming a field oxide layer in and on the semiconductor substrate, forming a gate oxide layer on the semiconductor substrate and adjacent to the field oxide layer, forming a first conductive layer on the field oxide layer and the gate oxide layer, forming an oxide layer on the first conductive layer, patterning the first conductive layer and the oxide layer to create a terminal edge on the field oxide layer in the boundary region, forming a second conductive layer over the semiconductor substrate, and patterning the first conductive layer, the second conductive layer and the oxide layer to form the split gate non-volatile memory cell in a cell array region of the semiconductor substrate. The patterning removes any conductive layer formed in the boundary region.
In accordance with one embodiment of the present invention, the patterning to form the split gate comprises forming a first masking pattern on a selected portion of the second conductive layer, wherein the first masking pattern does not cover a portion of the second conductive layer overlying the terminal edge; etching and removing portions of the second conductive layer, the oxide layer, and the first conductive layer not positioned under the first masking pattern to form the split gate in the cell array region; removing the first masking pattern; forming a second masking pattern to cover the split gate; and etching and removing any portion of the second conductive layer remaining in the boundary region.
In accordance with another embodiment of the present invention, the patterning to form a split gate comprises forming a first masking pattern to cover the second conductive layer overlying the oxide layer; etching and removing portions of the second conductive layer not covered by the first masking pattern; removing the first masking pattern; forming a second masking pattern over the semiconductor substrate, wherein the second masking pattern does not cover any portion of the second conductive layer in the boundary region, and wherein the second masking pattern covers a selected portion of the second conductive layer overlying the cell array region; and etching and removing portions of the second conductive layer, the interpoly oxide layer, and the first conductive layer not positioned under the second masking pattern to form the split gate.


REFERENCES:
patent: 5173436 (1992-12-01), Gill et al.
patent: 6054350 (2000-04-01), Hsieh et al.

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