Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-08-31
2001-05-08
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S382000, C438S384000
Reexamination Certificate
active
06228714
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to a method for manufacturing a nonvolatile memory device.
2. Description of the Related Art
The nonvolatile memory device is widely used in a computer or a memory card because information stored in a memory cell thereof is not erased even when power supply is turned off. A cell transistor of the nonvolatile memory device has a stacked gate structure in which a floating gate, an insulating layer, and a control gate electrode are sequentially formed on a tunnel oxide layer. In the stacked gate structures the floating gate stores electric charge and the control gate electrode serves as a wordline. However, a MOS transistor used for a peripheral circuit of the nonvolatile memory device includes a single gate electrode formed on a predetermined region of the gate insulating layer. The single gate electrode of the MOS transistor makes it difficult to form the gate pattern of both cell transistors through the same process.
A method for forming the single gate electrode of the MOS transistor formed on the peripheral circuit region and the gate pattern of the cell transistor formed on the cell array region using the same process is disclosed in Japanese Pat. No. 59,074,677A (“'677A patent”). According to the '677A patent, the gate pattern of the MOS transistor formed on the peripheral circuit region has the same stacked gate structure as that of the cell transistor. The '677A patent describes the MOS transistor as comprising first and second conductive layers and a dielectric layer interposed therebetween. The first and second conductive layers of the MOS transistor are electrically connected through a first contact hole passing through a predetermined region of the dielectric layer. Also, the second conductive layer is electrically connected to a metal interconnection through a second contact hole passing through a predetermined region of the interdielectric layer formed on the second conductive layer. The second conductive layer forms the gate pattern of the MOS transistor. The first conductive layer then is connected to a metal interconnection through the first and the second contact holes. As a result, the second conductive layer is interposed between the gate electrode of the MOS transistor forming the peripheral circuit and the metal interconnection. Thus, contact resistance between the first conductive layer and the second conductive layer deteriorates the propagation speed of an electric signal applied to the gate electrode of the MOS transistor. Also, according to the '677A patent, the second conductive layer is stacked on the first conductive layer such that forming a resistor using only the first conductive layer is difficult. The first conductive layer is generally formed of a polysilicon layer. When the resistor is formed of the first conductive layer, it is easy to control the resistance value of the resistor. Thus, it is difficult to form a resistor having a desired resistance value using the methodology disclosed in the '677A patent.
SUMMARY OF THE INVENTION
It is an object of the present invention to overcome the disadvantages of prior art nonvolatile semiconductor memory devices.
It is another object of the present invention to provide a method for manufacturing a nonvolatile memory device in which a gate pattern of a cell transistor and a gate pattern of a MOS transistor can be formed using the same process.
It is yet another object of the present invention to provide a method for manufacturing a nonvolatile memory device in which a gate electrode of the MOS transistor and a resistor can be connected directly to a metal interconnection.
A method for manufacturing a nonvolatile memory device having a cell array and a peripheral circuit region is provided. The cell array region includes a cell array having a plurality of cell transistors and the peripheral circuit region includes a resistor and a MOS transistor for driving the cell array. The method comprises forming a first conductive layer on a semiconductor substrate and forming a first conductive layer pattern by patterning the first conductive layer, forming the first conductive layer pattern includes forming an isolated resistor pattern in a resistor region of the peripheral circuit region. The method further includes sequentially forming a dielectric layer and a second conductive layer on the substrate and forming a second conductive layer pattern exposing a predetermined portion of the MOS transistor region and a whole area of the resistor region by patterning the second conductive layer. A gate pattern of each cell transistor and a gate pattern of the MOS transistor are formed in the cell array region and in the MOS transistor region, respectively, by sequentially patterning the second conductive layer pattern, the dielectric layer, and the first conductive layer pattern. The gate pattern of the each cell transistor includes a sequentially stacked floating gate, dielectric layer, and control gate. The gate pattern of the MOS transistor includes a sequentially stacked gate electrode, dielectric layer, and dummy gate electrode.
Forming a first conductive layer includes forming an isolation layer defining an active region of the substrate, forming a gate oxide layer on the active region of the peripheral circuit region, and forming a tunnel oxide layer on the active region of the cell array region. Forming the first conductive layer further includes forming the first conductive layer on the substrate after forming the gate oxide layer and the tunnel oxide layer. A first photoresist pattern is formed on the first conductive layer, the first photoresist pattern exposing a predetermined portion of the cell array region, covering the MOS transistor region, and covering a predetermined portion of the resistor region. Forming the first conductive layer pattern includes patterning the first conductive layer using the first photoresist pattern as a mask.
The first conductive layer may be formed of polysilicon and the dielectric layer may be formed of an oxide-nitride-oxide (O/N/O) layer. The second conductive layer may be polysilicon or a metal polycide layer. Preferably, the metal polycide layer is a tungsten polycide layer or a molybdenum polycide layer.
The method may further comprise forming a second photoresist pattern on the second conductive layer, the second photoresist pattern exposing the resistor region and the predetermined portion of the MOS transistor region and forming the second conductive layer pattern by patterning the second conductive layer using the second photoresist pattern as a mask.
The method may further comprise forming an interdielectric layer on the substrate after forming the gate pattern of each cell transistor and the gate pattern of the MOS transistor and forming a contact hole exposing the gate electrode of the MOS transistor and a predetermined portion of the first conductive layer of the resistor region by sequentially patterning the interdielectric layer and the dielectric layer. Finally, an interconnection covering the contact hole is formed.
According to a second embodiment of the present invention, a method for manufacturing a nonvolatile memory device having a cell array region and a peripheral circuit region. The cell array region includes an array of cell transistors and the peripheral circuit region includes a MOS transistor for driving the array of cell transistors and a resistor. The method comprises forming a first conductive layer on a substrate and forming a first conductive layer pattern in the same manner as described above. An isolated resistor pattern is formed of the first conductive layer pattern on a resistor region of the substrate. A dielectric layer and a second conductive layer are sequentially formed on substrate where the first conductive layer pattern is formed. The dielectric layer and the second conductive layer are formed of the same material layers as those described for
Booth Richard
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
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