Method for manufacturing stacked capacitor

Details Method for manufacturing stacked capacitor Method for manufacturing stacked capacitor

1999-06-18

2001-01-16

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S254000, C438S255000, C438S396000, C438S397000, C438S398000

Reexamination Certificate

active

06174769

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88106718, filed Apr. 27, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for manufacturing the capacitor of a semiconductor memory cell. More particularly, the present invention relates to a method for manufacturing a stacked capacitor of dynamic random access memory (DRAM).
2. Description of Related Art
As semiconductor device manufacturing progresses into the deep sub-micron range, dimensions of each semiconductor are all reduced. One consequence of this is the reduction of space for accommodating a capacitor having a conventional DRAM structure. In contrast, the size of software needed to operate a computer is forever growing, and hence the needed memory capacity must be increased. In the presence of these conflicting requirements, some changes have to be made regarding the design of DRAM capacitors.
A stacked capacitor structure is the principle type of capacitor to be used in manufacturing semiconductor memory. The stacked type of capacitor has been used for quite some time and continues to be used, even in sub-micron device fabrication.
Stacked capacitors can be roughly classified into crown-shaped, fin-shaped, cylinder-shaped or spread-out type. Although any of these stacked capacitors is able to satisfy the high density requirement of DRAMs, simply using such conventional structures to fabricate the capacitor can hardly go beyond 256 megabit (Mb) memory capacity.
However, the memory capacity can be promoted by increasing the surface area of the lower electrode of a crown-shaped capacitor so that higher memory capacity becomes possible. For example, the surface area of a capacitor can be further increased by selectively growing hemispherical grains (HSGs) on the low electrode.
FIGS. 1A through 1E
are cross-sectional views showing the progression of manufacturing steps in fabricating a conventional double-sided crown-shaped capacitor.
First, as shown in
FIG. 1A
, a substrate
100
having a number of devices (not shown) thereon is provided. Next, a silicon oxide layer
102
and a silicon nitride layer
104
are sequentially formed over the substrate
100
. The silicon oxide layer
102
serves as an inter-layer dielectric (ILD) while the silicon nitride layer
104
serves as an etching stop layer during the fabrication of the double-sided crown-shaped capacitor. Both the silicon oxide layer
102
and the silicon nitride layer
104
can be formed using a chemical vapor deposition (CVD) method, for example.
Thereafter, photolithographic and etching operations are conducted to form a contact opening
106
that passes through the silicon oxide layer
102
and the silicon nitride layer
104
. Next, a doped polysilicon plug is formed inside the contact opening
106
. The doped silicon plug can be formed by first depositing a layer of doped polysilicon (not shown in the figure) over the silicon nitride layer
104
and filling the contact opening
106
using a chemical vapor deposition (CVD) process. Then, the doped polysilicon layer above the silicon nitride layer
104
is removed using, for example, a reactive ion etching (RIE) method.
Next, as shown in
FIG. 1B
, an insulation layer
108
is formed over the silicon nitride layer
104
. The insulation layer
108
can be formed using, for example, a chemical vapor deposition (CVD) method. The insulation layer
108
is made, for example, from borophosphosilicate glass (BPSG). Thereafter, an opening
110
that exposes the contact opening
106
is formed using photolithographic and etching techniques.
Following, as shown in
FIG. 1C
, an amorphous silicon layer
112
conformal to the opening
110
and the surrounding insulation layer
108
is formed. The amorphous silicon layer
112
is formed using, for example, a low-pressure chemical vapor deposition (LPCVD) method.
Next, as shown in
FIG. 1D
, using the insulation layer
108
as a polishing stop layer, the amorphous silicon layer
112
above the insulation layer
108
are removed. Hence, only the amorphous silicon layer
112
a
inside the opening
110
remains. The method of removing portions of the amorphous silicon layer
112
includes a chemical-mechanical polishing (CMP) method.
Next, as shown in
FIG. 1E
, using the silicon nitride layer
104
as an etching stop layer, the insulation layer
108
above the silicon nitride layer
104
is removed using a wet etching method, for example. Hence, a crown-shaped capacitor structure is obtained.
Thereafter, hemispherical grains are formed on the exposed surface of amorphous silicon layer. Next, dielectric material is deposited to form a capacitor dielectric layer, and then an upper electrode is formed over the capacitor dielectric layer to form the double-sided crown-shaped capacitor. Since subsequent operations should be familiar to those skilled in the art of semiconductor manufacture, detailed descriptions are omitted here.
However, if the doping concentration in the amorphous silicon layer is insufficient in the manufacture of prior art, the hemispherical grains will have a undoped surface during its growth which results in a capacitance depletion effect. The capacitance depletion effect can contribute 25 percents degradation in capacity.
The capacitance depletion effect can be resolved due to an increment of the doping concentration in the amorphous silicon layer. Unfortunately, the high doping concentration in the amorphous silicon layer can inhibit the migration of silicon atoms resulting in the hemispherical grains being hard to form. The surface area-gain provided by hemispherical grains therefore decreases to affect the capacity of a capacitor.
SUMMARY OF THE INVENTION
The present invention provides a method of manufacturing a stacked capacitor that utilizes multi-amorphous silicon layer with different doping concentrations to resolve the capacitance depletion effect and the decrement of the area-gain of the hemispherical grains. Meanwhile, this invention utilizes a manufacture method of forming a trench line and a via applied in dual damascene process to get a double-sided double-crown-shaped capacitor with a more bottom electrode surface.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming a stacked capacitor. The method includes providing a substrate and forming a first dielectric layer over the substrate. A contact opening is formed in the first dielectric layer and a conductive plug is formed inside the contact opening. A second dielectric layer is formed over the substrate and a trench line is formed in the second dielectric layer. A via is formed in the second dielectric layer beneath the trench line and the conductive plug is exposed. An undoped first amorphous silicon layer is formed conformally to the trench line and the via. A doped second amorphous silicon layer is formed over the undoped first amorphous silicon layer. An undoped third amorphous silicon layer is formed over the doped second amorphous silicon layer. A photoresist layer is formed over the substrate to fill the trench line and the via. The photoresist layer, the undoped third amorphous silicon layer, the doped second amorphous silicon layer and the undoped first amorphous silicon layer above the second dielectric layer are removed using the second dielectric layer as a polishing stop layer. The photoresist layer filling in the trench line, the via and the second dielectric layer is removed thereafter. A plurality of hemispherical grains are formed over an exposed surface of the undoped first amorphous silicon layer and the undoped third amorphous silicon layer. And, a doping process to the hemispherical grains, the undoped first amorphous silicon layer and the undoped third amorphous silicon layer is performed.
According to this invention, a manufacture method of a trench line and a via applie

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