Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
1998-11-04
2001-04-10
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S015000, C438S025000, C438S106000, C438S107000, C438S612000, C438S613000, C438S127000, C257S780000, C257S781000, C257S782000, C257S783000
Reexamination Certificate
active
06214642
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to flip chip technology. In particular, the present invention is related to the interconnection between an integrated circuit chip and its corresponding substrate in flip chip device production. This invention is also related to the interconnection between an integrated circuit device and second level substrate such as a printed circuit board or card.
BACKGROUND OF THE INVENTION
An IC device is produced by electrically interconnecting an IC chip to an electronic substrate (hereinafter called substrate) to form one device. An electronic substrate is a non-conducting material containing single or multilayer electrically conducting traces for electrical connection. Flip chip device is produced by mounting an integrated circuit (IC) chip onto a substrate in a manner such that the active area of the IC chip and the substrate faces each other, and are electrically interconnected. Compared to other conventional methods of mounting, such as face-up wire bonding and face-up tape-automated bonding, flip chip technology provides the shortest possible leads, lowest inductance and highest frequency and density.
Flip Chip Technologies
edited by John H. Lau (1996) (Reference 1) gives an overview of the state of the art in this technology. In flip chip technology, the interconnection used to electrically connect the IC chip to the substrate include wire bumping, and solder bumping. Solder bumping can be performed on the IC chip surface and are thus useful for area array designs while wire bumping is commonly used for interconnection at the periphery of the IC chip.
Wire bonding involves the use of a wire bonder which has a wire fed through a tool called a capillary. The end of the wire is heated to a molten state where the surface tension of the liquid metal forms the shape of a ball. The capillary descends on the bond pad of the chip with a force to form a weld between the wire and the chip bond pad. Often, ultrasonic energy is included in the bonding process, in which case the process in known as thermosonic bonding. Typically the wirebond pads are situated over the periphery of the IC chips. In some instances such as in a memory chip, the bond pads are designed to be situated over the mid region of the chip. In either case, the bond pads cannot be formed over the active area of the chip.
Stud bumping is a modification of the wire bonding technique. Instead of a wire connection between the bonded IC chip and the I/O pad of the substrate, the wire is cut at the bonded ball, leaving behind a stud bump. Baba, S. in the IEEE 47th Electronic Components and Technology Conference Proceedings in 1997 pp. 268-273 (reference 2) describes the latest advances that have been made in the industry to develop a process for producing flip chips using stud bumping technology. In this reference, gold bumps are formed on the I/O pads at the periphery of the IC chip by wire bonding method, and then the bumps are pressed against the corresponding substrate pads. Typically, a conductive paste or anisotropic adhesive is added to or soldering is performed on the interconnections to complete the mechanical and electrical connection between the gold bumps and the substrate. Solder material such as solder paste or solder is commonly used. Mechanical contact pressure may also be employed. The chip is then encapsulated with an encapsulant such as thermosetting adhesive. Current state-of-the-art teaching, however, is that such wire bumping or stud bumping can only be applied to the non-active area of an IC chip, such as on the periphery, as discussed on page 58 of Reference 1. The active surface of a chip is the area corresponding to the region of the chip where the electronic elements such as transistors are fabricated. The main reason why stud bumping and wire bonding cannot be formed over the active area of the IC chip is because of the high risk of damage to the chip circuitry during the wire bonding process on the chip pads. Limiting the stud bumping to the inactive area of the chip severely limits the number of I/O pads which can be connected to the chip and also limit the direct access to the active areas of the chip, resulting in performance limitation. In addition, inactive areas have to be provided on the chip for bonding to occur, resulting in a larger surface area requirement of the chip, reducing the productivity of a given wafer size.
Solder bumping involves reflowing solder bumps which have been placed between solder wettable terminals on the IC chip and the connection pads on the substrate to form solder joints. Because solder bumping can be performed over the active surface of the chip, high density area array may be achieved, allowing smaller chip design and the manufacturing of packaging with very small footprints. Due to the advantages of area array chip designs, a great need is felt in the industry to search for more ways to produce flip chip packages and area array flip chips with maximized active areas.
OBJECT OF THE INVENTION
It is an object of the present invention to provide an area array flip chip device produced by stud bumping technology where the stud bump interconnections are over the active areas of the flip chip.
It is another object of the present invention to provide a process for stud bumping connection to the on the active surface of an IC chip.
SUMMARY OF THE INVENTION
The present invention provides a flip chip device which is produced using wire bonding technology whereby the stud bump interconnections can be made over the active area of the flip chip. The design and process for producing such a flip chip involves stud bumps which are bonded on the substrate, to give good electrical interconnections between the chip pads and the substrate pads. This completely eliminates the prior art limitation of not being able to have stud bump interconnections over the active area of the chip, and allows the stud bump interconnection method to be applied over the entire chip area. The invention can also be applied to the joining of an IC device or first level package to a second level substrate. In this application, the stud bump process acts as a replacement for the BGA process or the solder column grid array process. In another aspect of the present invention, the flip chip device produced using the stud bump interconnection according to the present invention may be electrically interconnected to a second level substrate to provide a stud bump flip chip package.
REFERENCES:
patent: 5436503 (1995-07-01), Kunitomo et al.
patent: 5521435 (1996-05-01), Mizukoshi
patent: 5598036 (1997-01-01), Ho
patent: 5641996 (1997-06-01), Omoya et al.
patent: 5666008 (1997-09-01), Tomita et al.
patent: 5705858 (1998-01-01), Tsukatamoto
patent: 5708304 (1998-01-01), Tomita
patent: 5834848 (1998-11-01), Iwasaki
patent: 5912507 (1999-06-01), Dunn et al.
Chen William T.
Lahiri Syamal Kumar
Chung David D.
Ho Lawrence Y. D.
Institute of Materials Research and Engineering
Lee Granville
Smith Matthew
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