Method of manufacturing dynamic random access memory

Details Method of manufacturing dynamic random access memory Method of manufacturing dynamic random access memory

1999-12-20

2001-03-13

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S595000

Reexamination Certificate

active

06200854

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing dynamic random access memory (DRAM) capable of reducing leakage current at junctions.
2. Description of the Related Art
In this information age, dynamic random access memory (DRAM) has become an indispensable component in many electronic products. As more memory capacity is demanded for each DRAM chip, the size of each DRAM device must decrease correspondingly.
To increase the density of DRAM devices, dimensions of each memory cell must decrease. However, reducing the dimensions of a DRAM cell also reduces the size of the capacitor within the memory unit, and hence is likely to reduce the capacitance of the capacitor. A lowered capacitance leads to a faster data loss resulting from an increase in charge leakage through an internal decay mechanism. Because the charges inside a DRAM storage capacitor leak out continuously, the DRAM storage capacitor must be refreshed from time to time to replenish charges. The frequency of refreshing is inversely proportional to capacitance of the capacitor. Because read or write operation cannot be carried out during a refreshing cycle, performance of the DRAM device eventually drops. Therefore, a method capable of producing a high-density and high performance DRAM device with a high capacitance capacitor and low level leakage is required.
Conventionally, the steps for producing DRAM includes forming shallow trench isolation (STI) structures in a substrate to mark out the active regions of memory cells, and then forming transistors in the active regions. After an isolating dielectric layer is formed over the transistors, bit line contact openings are formed in the dielectric layer. Bit lines that connect electrically with the respective transistor terminals through the bit contact openings are formed over the dielectric layer. After the formation of a second dielectric layer over the bit lines, node contact openings are formed and pass through the two dielectric layers. Finally, capacitors that connect electrically with the terminals of the respective transistors through the node contact openings are formed over the second dielectric layer.
In a conventional process of forming the DRAM device, internal stresses are likely to form when the STI structures are created. Dislocations and defects within the active regions of the semiconductor substrate can result in unwanted leakage current at junctions. In addition, since the concentration of dopants in the source/drain regions of the transistors is relatively high and reaches considerable depth and width, parasitic capacitance is usually high, thereby leading to an intensification of junction leakage current. Hence, the DRAM capacitors have to be refreshed more often.
In the meantime, due to the increase in level of device integration and reduction in line width, misalignment of contact opening now occurs more frequently, leading to a shift in contact position. Consequently, a portion of the charges in the node electrode moves towards the substrate, leading to the production of a leakage current and possibly device malfunction. To prevent the adverse effects of misalignment, stricter design rules must therefore be formulated.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method of fabricating DRAM capable of producing a DRAM device having a smaller junction leakage current, a lower charge-refreshing frequency and an increased device performance.
A second object of the invention is to provide a method of fabricating DRAM that involves simpler processing steps and demands less restrictive design rules. The storage nodes or the bit lines are electrically connected to respective source/drain regions via a contact pad, and hence processing is more predictable and errors due to misalignment can be avoided.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of fabricating DRAM. A semiconductor substrate having a plurality of device isolation structures therein is provided. A conductive layer, a metal silicide layer, a first cap layer and a second cap layer are sequentially formed over the substrate. The second cap layer, the first cap layer, the metal silicide layer and the conductive layer are patterned to form gate structures. A first oxide layer is formed over the sidewalls of the metal silicide layer and the conductive layer as well as over the exposed substrate. First spacers are formed on the sidewalls of the gate structures. A second oxide layer conformal to the profile of the substrate is formed. Second spacers are formed on the sidewalls of the second oxide layer. A third oxide layer is formed over the substrate. The second spacers, the second oxide layer and a portion of the first oxide layer are removed to expose a portion of the substrate. Contact pads that expose the second cap layer and a portion of the first spacers are formed, and then a first dielectric layer is formed over the entire substrate. Using the heat in subsequent processing operation, dopants within the contact pads are driven into the substrate on each side of the third oxide layer by diffusion, thereby forming source/drain regions. Bit lines that connect electrically with the contact pad through a contact in the first dielectric layer are formed. A second dielectric layer is formed over the entire substrate. A storage node electrode that connects electrically with the contact pad through a contact in the second dielectric layer is formed.
In the embodiment of the invention, the third oxide layer is formed in the space between the gate structures. Hence, the area of the subsequently formed source/drain junction region can be controlled. In addition, since the source/drain regions are formed by the diffusion of dopants from the contact pads into the substrate in a subsequent heating operation, the concentration of dopants is lower and can reach only a shallow depth. Hence, junction leakage current of the device is greatly reduced.
Furthermore, the bit lines and the storage node electrode are electrically connected to the respective source/drain regions through a contact pad, hence the processing steps are more predictable and errors due to misalignment can be avoided.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 6057196 (2000-05-01), Gau
patent: 6093641 (2000-05-01), Park

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