Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1992-07-29
1994-06-28
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
36518906, 36523008, 36518901, G11C 700
Patent
active
053253280
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
This invention relates to, for example, a semiconductor memory device having an ATD (Address Transition Detector) that produces a signal according to the change of address, and more particularly to the output circuit of a sense amplifier.
BACKGROUND ART
FIG. 6 illustrates an important part of a conventional semiconductor memory device such as an EPROM. This semiconductor memory device comprises: for example, an address buffer 31 that stores the data read address signal temporarily; an X-decoder 32 and a Y-decoder 33 that decode the address signal from the address buffer 31; a Y-selector 34 that receives the output of the Y-decoder 33; a memory cell unit 35 from which a particular cell is selected depending o the outputs of the Y-selector 34 and X-decoder 32; a sense amplifier 36 that amplifies the signal read out of the memory cell unit 35 and supplied from the Y-selector 34 and produces a data signal with a specified level; a pulse generator circuit (ATD) 37 that senses the change of address signal in the address buffer 31, generates a specified pulse signal (hereinafter, referred to as an equalizer pulse signal), and supplies it to the sense amplifier 36; an input/output buffer circuit 38 that outputs the data signal from the sense amplifier 36; a data input section 39 that drives transistors (not shown) in the Y-selector 34 depending on the data from the input/output buffer circuit 38; and a controller 40 that controls the sense amplifier 36, pulse generator circuit 37, input/output buffer circuit 38, and data input section 39 on the basis of the chip enable signal /CE, output enable signal /OE, program (write) signal /PGM, and power supply V.sub.pp.
The memory cell unit 35 is composed of, for example, a referential EPROM and is designed to allow the simultaneous reading of signals of different levels.
The sense amplifier 36 is designed to produce signals of a specified level by, for example, three-stage amplification of different-level signals from the memory cell unit 35 via the Y-selector 34. Each of the first through third stage amplifying section is made up of a pair of differential amplifiers and a transfer gate circuit that equalizes the outputs of the differential amplifier pair to the same level on the basis of the equalize pulse signal from the pulse generator circuit 37.
FIG. 7 illustrates the construction of the third-stage amplifying section and output circuit.
The differential amplifiers 36a and 36b compare the signals from the second-stage amplifying section (not shown) for potential difference and judges whether the signal is at the "1" or "0" level. These differential amplifiers 36a and 36b are supplied with input signals so as to each produce signals of different levels, that is, the output level of the differential amplifier 36b is "0" when the output level of the differential amplifier 36a is "1". Specifically, the input signal V.sub.in1 is supplied to both the non-inverted input terminal of the differential amplifier 36a and the inverted terminal of the differential amplifier 36b, while the input signal Vin2 is supplied to both the non-inverted input terminal of the differential amplifier 36b and the inverted terminal of the differential amplifier 36a.
The output terminals of the differential amplifiers 36a and 36b are connected to inverter circuits 36c and 36d, respectively. Connected across the output terminals of the amplifiers 36a and 36b is a transfer gate 36e consisting of a p-channel transistor P1 and an n-channel transistor N1 connected in parallel. The gates of the n-channel transistor N1 and p-channel transistor P1 are supplied with the equalize pulse signals EQ and /EQ from the pulse generating circuit 37, respectively.
The operation of this arrangement will be explained, referring to FIG. 8.
Before the change of address ADD, the potential Va of the node a between the differential amplifier 36a and inverter circuit 36c is at the "1" level, the potential Vb of the node b between the differential amplifier 36b and inverter circuit 36d is at the "0" level
REFERENCES:
patent: 4891792 (1990-01-01), Hanamura et al.
patent: 5043944 (1991-08-01), Nakamura et al.
patent: 5058062 (1991-10-01), Wada et al.
patent: 5126974 (1992-06-01), Sasaki et al.
patent: 5126974 (1992-06-01), Sasaki et al.
IBM Technical Disclosure Bulletin, vol. 32, No. 4A, Sep. 1989, pp. 116-118.
Haraszti, "CMOS/SOS Memory Circuits for Radiation Environments", IEEE Journal of Solid-State Circuits, vol. SC-13, No. 5, Oct. 1978, pp. 669-676.
Atsumi Shigeru
Muroya Yukinori
Kabushiki Kaisha Toshiba
LaRoche Eugene R.
Le Vu A.
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