Methods of fabricating integrated circuit field effect transisto

Details Methods of fabricating integrated circuit field effect transisto Methods of fabricating integrated circuit field effect transisto

1996-07-29

1998-01-06

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438307, H01L 21265

Patent

active

057054401

ABSTRACT:
A integrated circuit field effect transistor is formed with device isolation regions disposed on opposite sides of the transistor, each of which include a shallow insulation-filled trench region which abuts an insulating region underlying an active region of the transistor. A pair of spaced apart insulation-filled trench regions are formed in a semiconductor substrate at a surface of the substrate. An insulated gate is formed on the substrate between and separated from the insulation-filled trench regions. Spaced apart source and drain insulating regions are formed in the substrate, a respective one of which is disposed between the insulated gate and a respective one of the insulation-filled trench regions. Corresponding spaced apart source and drain regions are then formed on the spaced apart source and drain insulating regions. The insulated gate is formed overlying a channel region disposed between lightly doped source and drain regions.

REFERENCES:
patent: 4593459 (1986-06-01), Poppert et al.
patent: 4683637 (1987-08-01), Varker et al.
patent: 5480832 (1996-01-01), Muira et al.
patent: 5488010 (1996-01-01), Wong
patent: 5491099 (1996-02-01), Hsu
patent: 5492858 (1996-02-01), Bose et al.

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