Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-08-24
2000-01-25
Whitehead, Jr., Carl
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438257, 438571, 438583, 438655, H01L 21336
Patent
active
060177969
ABSTRACT:
A semiconductor fabrication method for fabricating a flash EEPROM (electrically erasable and programmable read-only memory) device uses STI (shallow-trench isolation) technique to form the field oxide isolation layers so as to make the EEPROM device suitable for fabrication at the submicron level of integration. By this method, the first step is to prepare a semiconductor substrate. Next, a plurality of field oxide isolation layers are formed through the STI technique to define active region in the substrate. After this, at least one gate structure is formed within the active region, which includes a tunnel oxide layer, a first conductive layer serving as a floating gate, a dielectric layer, a second conductive layer serving as a control gate, and a topping layer. Subsequently, an ion-implantation process is performed to form source/drain regions beside the gate structure. A sidewall spacer is then formed on the sidewall of the gate structure. Next, a metallization layer is formed over the entire substrate and then an insulating layer is formed over the metallization layer. The insulating layer is then selectively removed in such a manner that the remaining part thereof covers the source region and the field oxide isolation layers neighboring the source region. Finally, all the part of the metallization layer that is uncovered by the remaining part of the insulating layer is entirely removed.
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Chen Hwi-Huang
Hong Gary
Duong Khanh
Jr. Carl Whitehead
United Semiconductor Corp.
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