Data output buffer circuit with precharged bootstrap circuit

Details Data output buffer circuit with precharged bootstrap circuit Data output buffer circuit with precharged bootstrap circuit

1991-01-22

1993-08-31

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Precharge

36518905, G11C 1140, G11C 700

Patent

active

052415023

ABSTRACT:
A data output buffer circuit includes a pair of data lines respectively applied with a noninverted data signal and an inverted data signal and an output gate circuit for gating the noninverted and inverted data signals in response to an output enable signal. A pull-up/pull-down NMOS transistor pair is connected in series between a first supply voltage and a ground voltage. A supply voltage converter circuit generates a constant second supply voltage so long as said first supply voltage is above a predetermined minimum level. A bootstrap circuit is precharged by the second supply voltage for driving the pull-up NMOS transistor with a boosted voltage level when the non-inverted data signal is a logic "HIGH" state. The bootstrap circuit includes a first NMOS transistor, a main capacitor, a secondary capacitor, second and third NMOS transistors to precharge the secondary capacitor, an overcurrent limit circuit for limiting overcurrent into the secondary capacitor, a first CMOS inverter for transferring the boosted voltage from the main capacitor to a gate electrode of the pull-up transistor during the logic "HIGH" state, and for transferring the ground voltage during a logic "LOW" state, and a second CMOS inverter for transferring the second supply voltage to a second terminal of the main capacitor during the logic "HIGH" state, and for transferring the ground voltage thereto during the logic "LOW" state.

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