Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1999-01-04
1999-11-02
Le, Vu A.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365233, 3652335, G11C 700
Patent
active
059782811
ABSTRACT:
A postamble corruption protection circuit is provided that disables data latching by a first falling edge register following a data strobe (DQS) falling edge until the data within the first falling edge register has been latched into a second falling edge register in response to a second falling edge register latching signal. Specifically, data latching by the first falling edge register is disabled following each DQS falling edge and is enabled following each second falling edge register latching signal. Data latching of the first falling edge register is controlled by the output of a set/reset register which is gated with the DQS to form a first falling edge register latching signal. When the set/reset register is set, data latching is enabled and when the set/reset register is reset, data latching is disabled. The set/reset register is set in response to a second falling edge register latching signal and is reset in response to a DQS falling edge.
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Anand Darren L.
Tamlyn Robert
International Business Machines - Corporation
Le Vu A.
Walsh Robert A.
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