Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1998-09-03
2000-09-26
Quach, T. N.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438632, 438645, 438687, 438672, H01L 2144
Patent
active
061242055
ABSTRACT:
An improved semiconductor device structure comprises insertion of a semiconductor wafer into a high-pressure heated chamber and the deposition of a low-melting point aluminum material into a contact hole or via and over an insulating layer overlying a substrate of the wafer. The wafer is heated up to the melting point of the aluminum material and the chamber is pressurized to force the aluminum material into the contact holes or vias and eliminate voids present therein. A second layer of material, comprising a different metal or alloy, which is used as a dopant source, is deposited over an outer surface of the deposited aluminum material layer and allowed to diffuse into the aluminum material layer in order to form a homogenous aluminum alloy within the contact hole or via. A semiconductor device structure made according to the method is also disclosed.
REFERENCES:
patent: 5355020 (1994-10-01), Lee et al.
patent: 5512512 (1996-04-01), Isobe
patent: 5527561 (1996-06-01), Dobson
patent: 5985763 (1999-11-01), Hong et al.
patent: 5998296 (1999-12-01), Saran et al.
Dixit et al., "A Novel High Pressure Low Temperature Aluminum Plug Technology For Sub-0.5 .mu.m Contact/Via Geometries", IEDM, Dec. 1994, pp. 105-108.
Dixit et al., "A Novel 0.25 .mu.m Via Plug Process Using Low Temperature CVD AI/TiN", IEDM 95, Dec. 1995, pp. 1001-1003.
Dixit et al., "A reactively sputtered coherent TiN process for sub-0.5 .mu.m technology", SPIE, vol. 2090 Multilevel Interconnection; pp. 12-21, 1993.
Dixit et al., "An Integrated Low Resistance Aluminum Plug and Low-k Polymer Dielectric For High Performance 0.25 .mu.m Interconnects", 1996 Symposium on VLSI Technology Digest of Technical Papers, pp. 86-87, 1996.
Dixit et al., "Application of High Pressure Extruded Aluminum to ULSI Metallization", Semiconductor International, pp. 79-85, Aug. 1995.
Jain et al., "Chemical mechanical planarization of multilayer dielectric stacks", SPIE, vol. 2335, pp. 2-11, 1993.
Mizobuchi et al., "Application of Force Fill Al-Plug Technology to 64Mb DRAM and 0.35 .mu.m Logic", 1995 Symposium on VLSI Technology Digest of Technical Papers, 45-46.
Ting et al., "Effect of Via Etch Profile and Barrier Metal on Electromigration Performance of W-filled Via Structure in TiN/A1Cu/TiN Metallization", Mat. Res. Soc. Symp. Proc., vol. 391, pp. 453-458, 1995.
Micro)n Technology, Inc.
Quach T. N.
LandOfFree
Contact/via force fill process does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Contact/via force fill process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Contact/via force fill process will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2099779