Frequency divider employing multiple stages of master/slave flip

Details Frequency divider employing multiple stages of master/slave flip Frequency divider employing multiple stages of master/slave flip

1991-04-03

1992-12-15

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Particular transfer means

Including logic circuit

377114, 377115, 377 47, 377 48, H03K 2106

Patent

active

051724006

ABSTRACT:
A frequency divider includes at least three master-slave flip-flops which are connected to each other in stages, each stage including a master flip-flop and a slave flip-flop, to construct a 1/N frequency divider. At least two outputs whose periods are the same but phases are different are taken out from a master flip-flop and a slave flip-flop and combined to obtain a 1/(N/2) divided output signal. As a result, a divided output signal whose period does not vary with time is obtained and, when the N is an even number, an output signal with a duty ratio of 1/2 is obtained. A pulse signal former includes a differential amplifier to which two signals whose periods and pulse widths are the same but phases are shifted by a pulse width and an output obtained by comparing those two signals is output from the pulse signal former. As a result, an output signal whose duty ratio is 1/2 is obtained.

REFERENCES:
patent: 3943379 (1976-03-01), McGuffin
patent: 4601049 (1986-07-01), Wilhelm et al.
patent: 4606059 (1986-08-01), Oida
patent: 4730349 (1988-03-01), Wilhelm et al.
patent: 4799040 (1989-01-01), Yanagi
patent: 4815114 (1989-03-01), Pham
patent: 4926451 (1990-05-01), Yoshihara et al.

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