Method of forming a lower electrode of a capacitor in a DRAM cel

Details Method of forming a lower electrode of a capacitor in a DRAM cel Method of forming a lower electrode of a capacitor in a DRAM cel

1999-06-28

2000-09-26

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

439398, H01L 218242

Patent

active

061241660

ABSTRACT:
The present invention relates to a method of forming a lower electrode of a capacitor on a DRAM cell in a semiconductor wafer for increasing a surface area of the lower electrode. It is achieved by forming a second dielectric layer on a first polysilicon layer which comprises a plurality of doped horizontal layers along a vertical direction. Because dopant densities of the doped horizontal layers alternate in a high and low sequence, when forming a second polysilicon layer on the second dielectric layer, the second polysilicon layer will have many hemispherical grains on the vertical side wall of the second dielectric layer. This will result in an increased surface area of the lower electrode.

REFERENCES:
patent: 6037219 (2000-03-01), Lin et al.
patent: 6037220 (2000-03-01), Chien et al.

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