Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1997-06-23
2000-06-13
Palys, Joseph E.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714735, 714736, 714737, 710 15, G06F 1100
Patent
active
060761806
ABSTRACT:
A method for testing an IDE controller with random constraints, the method comprising: providing an IDE controller model having a primary and a secondary channel and a host interface; transmitting data patterns to a primary and a secondary device model; receiving the data patterns from the primary and secondary device models; arbitrating the transfer of the data patterns to and from the primary and secondary device models; and determining whether the data patterns returned from the primary and secondary device models match expected values.
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Mai Rijue
Micron Electronics Inc.
Palys Joseph E.
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