Methods of fabrication DRAM transistor cells with a self-aligned

Details Methods of fabrication DRAM transistor cells with a self-aligned Methods of fabrication DRAM transistor cells with a self-aligned

Filed on

1998-05-11

Date issued

2000-06-13

Examiner

Tsai, Jey

Patent Class

Semiconductor device manufacturing: process

SubClass

Making field effect device having pair of active regions...

SubSubClass

Having insulated gate

Other Related Categories

438254, H01L 278242

Type

Patent

Status

active

Patent number

060749180

Description

ABSTRACT:
A DRAM cell is formed by forming a capped gate line on a substrate, including a gate line insulation layer on the substrate, a gate line on the gate line insulation layer and a gate line cap covering top and sidewall portions of the gate line. Spaced apart source/drain regions are formed in the substrate on opposite sides of the gate line. A dielectric region is formed covering the capped electrode. A storage electrode plug is formed extending from a surface of the dielectric region through the dielectric region and along a first sidewall portion of the gate line cap to contact a first of the source/drain regions. A channel electrode is formed extending from the surface of the dielectric region through the dielectric region and along a second sidewall portion of the gate line cap to contact a second of the source/drain regions. The channel electrode may include a channel line formed on a channel line insulation layer on the dielectric region and having a channel line extension extending through the channel line insulation layer into the dielectric region, and a channel electrode plug extending from the channel line extension to the second source/drain region.

REFERENCES:
patent: 3749610 (1973-07-01), Swann et al.
patent: 4985718 (1991-01-01), Ishijima
patent: 5279989 (1994-01-01), Kim
patent: 5335138 (1994-08-01), Sandhu et al.
patent: 5383088 (1995-01-01), Chapple-Sokol et al.
patent: 5569948 (1996-10-01), Kim
patent: 5763286 (1998-06-01), Figura et al.

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