Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
2000-01-05
2000-11-14
Smith, Matthew
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438633, 438798, 438788, 438792, H01L 214763
Patent
active
061469882
ABSTRACT:
Cu diffusion between Cu and Cu alloy interconnect members, e.g., lines, in a silicon oxide inter-layer dielectric is avoided or substantially reduced by converting an upper portion of the silicon oxide inter-layer dielectric between neighboring lines to silicon oxynitride and then depositing a capping layer. Embodiments include filling damascene trenches in a silicon oxide inter-layer dielectric with Cu or a Cu alloy, CMP to effect planarization such that the upper surfaces of the lines are substantially coplanar with the upper surface of the inter-layer dielectric and treating the exposed surfaces with a high strength ammonia plasma to ion bombard the exposed inter line silicon oxide with nitrogen atoms, thereby converting the upper portion to silicon oxynitride, while simultaneously removing or substantially reducing surface oxides on the lines. A silicon nitride capping layer is then deposited.
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Passivation of copper by silicide formation in dilute silane--S. Hymes and S. P. Murarka, Rensselaer Polytechnic Institute Troy, New York 12180--C. Shepard and W. A. Lanford, State University of New York, Albany, New York 12222--Received Jul. 29, 1991: (accepted for publication Jan. 25, 1992) pp. 4623-4625.
Ngo Minh Van
Nogami Takeshi
Advanced Micro Devices , Inc.
Hullinger Robert A.
Smith Matthew
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