Method of making monos flash memory for multi-level logic

Details Method of making monos flash memory for multi-level logic Method of making monos flash memory for multi-level logic

1997-10-06

1998-12-22

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438266, 438296, H01L 218247

Patent

active

058518819

ABSTRACT:
The present invention provides a structure and method of manufacturing split gate MONOS multi-level logic memory device. The memory device has a poly stacked gate transistor 20A in series with a MONOS transistor 24A. The device has a novel operation to achieve multi-level memory storage (e.g., 4 voltage states). The method begins by forming a tunnel oxide layer 30 on the surface of a semiconductor substrate 10. The substrate having a stacked gate channel area 20 and a MONOS channel area 24 in the active regions. A poly floating gate electrode 32 is formed over the stacked gate channel region 20. A ONO layer having a memory nitride layer is formed over the floating gate 32 and the tunnel oxide layer over the MONOS channel region 24. A control gate electrode 44 is formed over the ONO layer 41 spanning across the poly floating gate electrode 32 and the MONOS channel region 24. Source/drain regions 50 51 are formed in the substrate. A poly flash transistor 20A and a MONOS flash transistor 24A combine to form the 4 level logic memory cell of the invention.

REFERENCES:
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patent: 5515321 (1996-05-01), Hazama
patent: 5559048 (1996-09-01), Inoue
"A 1-Mb EEPROM With a Monos Memory Cell For a Semi-conductor Disk Application" IEEE Journal of Solid State Circuits, vol. 26, No. 4, Apr. 1991, p. 498.

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