Method to manufacture dual damascene structures by utilizing sho

Details Method to manufacture dual damascene structures by utilizing sho Method to manufacture dual damascene structures by utilizing sho

1998-08-19

2000-08-15

Whitehead, Jr., Carl

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438618, 438634, 438638, H01L 214763

Patent

active

061036161

ABSTRACT:
A method of manufacturing semiconductor devices wherein a partially completed semiconductor device having a first and second layer of interlayer dielectric and a first and second etch stop layer has the second etch stop layer masked and etched with an etch pattern having dimensions of the trench structure to be formed in the second interlayer dielectric. The second layer dielectric and first etch stop layer are then masked and etched with an etch pattern having dimensions of the via structure to be formed in the first interlayer dielectric. The remaining portions of the photoresist is removed and exposed portions of the second layer of interlayer dielectric and the first layer of interlayer dielectric are then etched simultaneously. The via structure and trench structure are then simultaneously filled with a conductive material.

REFERENCES:
patent: 5635423 (1997-06-01), Huang et al.
patent: 5741626 (1998-04-01), Jain et al.
patent: 5916823 (1999-06-01), Lou et al.
patent: 6037213 (2000-03-01), Shih et al.
patent: 6037664 (2000-03-01), Zhao et al.

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