Nitride disposable spacer to reduce mask count in CMOS transisto

Details Nitride disposable spacer to reduce mask count in CMOS transisto Nitride disposable spacer to reduce mask count in CMOS transisto

1999-03-17

2000-08-15

Fahmy, Wael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438230, 438232, 438305, 438306, H01L 218238

Patent

active

061035637

ABSTRACT:
Semiconductor devices of different conductivity types are formed on a semiconductor substrate using a minimal number of critical masks. Embodiments include forming conductive gates on the main surface of the semiconductor substrate, and disposable nitride spacers on the sidewalls of the gates. A photoresist mask is then formed on gates and portions of the main surface intended to be implanted with impurities of a first conductivity type. Moderate or heavy source/drain implants of a second impurity type are then formed in the substrate, the disposable spacers on the unmasked gates are then removed, and lightly or moderately doped source/drain extension implants of the second impurity type are formed in the substrate. The first mask is then removed and a second photoresist mask is formed on the previously uncovered gates and implanted portions of the main surface. Moderate or heavy source/drain implants with impurities of the first conductivity type are then formed, the remaining disposable spacers are removed, and lightly or moderately doped source/drain extension implants of the first conductivity type formed. By using disposable spacers, the critical masking steps for source/drain ion implantation can be reduced to two, thereby reducing production costs and increasing manufacturing throughput.

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K. Noda et al., "A 2.9 .mu.m.sup.2 Embedded SRAM Cell with Co-Salicide Direct-Strap Technology for 0.18 .mu.m High Performance CMOS Logic", IEDM Technical Digest, Dec., 1997, pp. 847-850.

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