Methods of fabricating memory cells with reduced area capacitor

Details Methods of fabricating memory cells with reduced area capacitor Methods of fabricating memory cells with reduced area capacitor

1998-02-19

2000-06-27

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438454, 438653, 438656, 438666, 438685, 257295, 257296, H01L 2176, H01L 2144, H01L 27108, H01L 2978

Patent

active

060806168

ABSTRACT:
A memory cell is formed including an insulation region on the substrate and a transistor including a gate on the substrate and a source/drain region in the substrate disposed between the gate and the insulation region. The cell also includes a capacitor including an electrode overlying the insulation region, the electrode having a lateral surface adjacent the source/drain region. A conductive interconnecting region is formed on the substrate and extends from the source/drain region to contact the lateral surface of the first electrode of the capacitor. The capacitor may include a first electrode on the insulation region, a dielectric region on the first electrode, and a second electrode on the dielectric region. The first electrode preferably is platinum and the dielectric region preferably is a ferroelectric material such as lead zirconate titanate (PZT) or Ba.sub.x Sr.sub.1-x TiO.sub.3 (BST). The first electrode preferably has a lateral surface, and the conductive interconnecting region extends to contact the lateral surface of the first electrode. The first electrode preferably has a top surface adjacent the lateral surface, and the cell preferably further comprises an insulation region on the top surface of the first electrode which laterally separates the dielectric region and the second electrode from the conductive interconnecting region.

REFERENCES:
patent: 5369296 (1994-11-01), Kato
patent: 5578867 (1996-11-01), Argos
patent: 5719416 (1998-02-01), Yoshimori
patent: 5866926 (1999-02-01), Takenaka

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