Method of forming asymmetrically doped source/drain regions

Details Method of forming asymmetrically doped source/drain regions Method of forming asymmetrically doped source/drain regions

1997-01-17

1999-05-18

Booth, Richard A.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438305, H01L21/336

Patent

active

059045280

ABSTRACT:
Asymmetrically doped source/drain regions of a transistor are formed employing protective insulating layers to prevent a portion of the gate electrode from receiving an excessive impurity implantation dose and penetrating through the underlying gate insulating layer into the semiconductor substrate. Sidewall spacers are employed during heavy implantation.

REFERENCES:
patent: 5200351 (1993-04-01), Hadjizadeh-Amini
patent: 5286664 (1994-02-01), Horiuchi
patent: 5413969 (1995-05-01), Huang
patent: 5573965 (1996-11-01), Chen et al.
patent: 5602055 (1997-02-01), Nicholls et al.
patent: 5759897 (1998-06-01), Kadosh et al.
Horiuchi et al., "An Asymmetric Sidewall Process of High Performance LDD MOSFET's," IEEE Transactions on Electron Devices, vol. 41, No. 2, Feb. 1994, pp. 186-190.

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