Stack gate flash memory cell featuring symmetric self aligned co

Details Stack gate flash memory cell featuring symmetric self aligned co Stack gate flash memory cell featuring symmetric self aligned co

1998-10-23

2000-03-14

Booth, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438264, H01L 218247

Patent

active

060372230

ABSTRACT:
A process for fabricating a flash memory cell, featuring self-aligned contact structures, overlying and contacting, self-aligned source, and self-aligned drain regions, located between stack gate structures, has been developed. The stack gate structures, located on an underlying silicon dioxide, tunnel oxide layer, are comprised of: a capping insulator shape; a polysilicon control gate shape; an inter-polysilicon dielectric shape; and a polysilicon floating gate shape. The use of self-aligned contact structures, and self-aligned source regions, allows increased cell densities to be achieved.

REFERENCES:
patent: 5631179 (1997-05-01), Sung et al.
patent: 5705438 (1998-01-01), Tseng
patent: 5734607 (1998-03-01), Sung et al.
patent: 5741719 (1998-04-01), Kim
patent: 5763303 (1998-06-01), Liaw et al.
patent: 5766992 (1998-06-01), Chou et al.
patent: 5821143 (1998-10-01), Kim et al.
patent: 5899722 (1999-05-01), Huang
patent: 5998252 (1999-12-01), Huang

Affiliated with

Also associated with

Rating

Stack gate flash memory cell featuring symmetric self aligned co does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Stack gate flash memory cell featuring symmetric self aligned co, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stack gate flash memory cell featuring symmetric self aligned co will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-168771