Bit line precharge circuit with reduced standby current

Details Bit line precharge circuit with reduced standby current Bit line precharge circuit with reduced standby current

1998-06-10

1999-11-30

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Precharge

365149, 36518911, G11C 700

Patent

active

059954310

ABSTRACT:
A circuit is designed with a memory array (102) having a plurality of memory cells arranged in rows and columns (204, 206, 210, 212). The memory array has a plurality of bit line pairs (202, 208, 282, 284) with each bit line pair connected to a respective column of memory cells and a bit line reference terminal (254). A control circuit (700) produces a control signal, the control signal having a first voltage for a first time, a second voltage for a second time and a third voltage for a third time. A precharge circuit (350, 352) connects at least one bit line pair to the bit line reference terminal, responsive to the first voltage for the first time and the second voltage for the second time. The precharge circuit disconnects the at least one bit line pair from the bit line reference terminal, responsive to the third voltage for the third time.

REFERENCES:
patent: 5612912 (1997-03-01), Gillingham
patent: 5666318 (1997-09-01), Takai
patent: 5710738 (1998-01-01), Tai
patent: 5761123 (1998-06-01), Kim et al.

Affiliated with

Also associated with

Rating

Bit line precharge circuit with reduced standby current does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bit line precharge circuit with reduced standby current, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bit line precharge circuit with reduced standby current will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1681894