Method for forming a DRAM cell electrode

Details Method for forming a DRAM cell electrode Method for forming a DRAM cell electrode

1997-05-19

1999-11-30

Whitehead, Jr., Carl

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438243, 438253, 438381, 438386, 438396, H01L 218242

Patent

active

059941812

ABSTRACT:
A polysilicon layer is subsequently deposited on the dielectric layer by using CVD. Next, photolithography and etching process are used to etch the doped polysilicon layer, and form a bottom electrode of DRAM cell capacitor with U shape in cross section view. The next step of the formation is the deposition of a dielectric film along the surface of the bottom electrode of DRAM cell capacitor. Typically, the dielectric film is preferably formed of high dielectric film such as tantalum oxide (Ta.sub.2 0.sub.5). A conductive layer is deposited over the dielectric film. The conductive layer is used as the top storage node and is formed of titanium nitride(TiN). The methods of forming the top storage node, including sputtered-TiN, collimated-sputtering TiN, and CVD/MOCVD-TiN deposition. The purposes of sputtered-TiN and collimated-sputtering TiN processes can improve the poor step coverage of deep well of bottom electrode of DRAM cell capacitor and protect the Ta.sub.2 0.sub.5 from C, Cl, F contamination during CVD/MOCVD-TiN deposition process.

REFERENCES:
patent: 5279985 (1994-01-01), Kamiyama
patent: 5396096 (1995-03-01), Wolters et al.
patent: 5612560 (1997-03-01), Chivukula et al.
patent: 5670808 (1997-09-01), Nishihori et al.
patent: 5804479 (1998-09-01), Aoki et al.
patent: 5854104 (1998-12-01), Onishi et al.

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