Method of making dual isolation regions for logic and embedded m

Details Method of making dual isolation regions for logic and embedded m Method of making dual isolation regions for logic and embedded m

1997-06-12

1999-01-12

Booth, Richard A.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438258, 438425, 438296, 438297, H01L 218242, H01L 21336, H01L 2176

Patent

active

058588302

ABSTRACT:
A method for forming thick field oxide regions, to be used for isolation in MOSFET memory regions, while also forming insulator filled, narrow trenches, to be used for isolation purposes in MOSFET logic regions, has been developed. The fabrication process features initially creating thick field oxide regions, in the MOSFET memory region, obtained via thermal oxidation procedures, followed by creation of a narrow trench opening, in the MOSFET logic region. An ozone aided, silicon oxide, CVD deposition, is used to fill the narrow trench openings, followed by a selective chemical mechanical polishing procedure, used to remove unwanted regions of silicon oxide layer, creating an insulator filled, narrow trench isolation, in the MOSFET logic region.

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