Synchronous semiconductor memory device in which current consume

Details Synchronous semiconductor memory device in which current consume Synchronous semiconductor memory device in which current consume

1997-10-29

1999-03-09

Hoang, Huan

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365233, 36523008, G11C 700

Patent

active

058809988

ABSTRACT:
An external clock enable signal is taken in accordance with a first internal clock signal from clock buffer circuit from which an input buffer enable signal is generated to be input to input buffer circuit. Current path in the input buffer circuit is shut off in accordance with the input buffer enable signal. Since the state of the input buffer enable signal is changed in synchronization with the rise of the internal clock signal, the set up time of the external signal can be sufficiently ensured while current consumption of input buffer circuit can be reduced.

REFERENCES:
patent: 5229966 (1993-07-01), Ohsawa et al.
patent: 5469386 (1995-11-01), Obara
patent: 5559752 (1996-09-01), Stephens, Jr. et al.
"A 100MHz Dual-Bank 16Mbit Synchronous DRAM", Yasuhiro Konishi et al, Mitsubishi Denki Giho: vol. 69, No. 3, pp. 51-53 Mar. (1995).

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