Process for manufacture of MOS gated device with self aligned ce

Details Process for manufacture of MOS gated device with self aligned ce Process for manufacture of MOS gated device with self aligned ce

1997-10-22

2000-03-28

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438268, 438270, 438138, 438527, H01L 21336

Patent

active

060431261

ABSTRACT:
An MOS-gated power semiconductor device is formed by a process in which a self-aligned device cell is formed without any critical alignments. A sidewall spacer is used to mask the etching of a depression in the silicon to reduce the number of critical alignment steps. An optional selectively formed metal connects the polysilicon layer to the P+ and N+ diffusion regions. The sidewall spacer, in combination with the selectively formed metal, prevents impurities from diffusing to the parasitic DMOS channels and inverting them to cause leakage. A termination structure may also be formed by this process.

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