Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1997-10-23
1999-03-09
Chaudhuri, Olik
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438691, 438701, H01L 2176
Patent
active
058800050
ABSTRACT:
A method for creating a tapered profile insulator shape, on an underlying silicon nitride layer, using a photoresist shape as a mask, has been developed. A two step dry etching procedure is used, featuring a first dry etching phase, using an etching chemistry comprised of argon, CHF.sub.3 and CF.sub.4, resulting in a tapered profile insulator shape, underlying the photoresist shape. A second dry etching phase, exhibiting high etch rate selectivity between insulator layer and underlying silicon nitride, via use of an etching chemistry comprised of argon, CHF.sub.3, CH.sub.2 F.sub.2, and CH.sub.3 F, is used to remove residual insulator layer from the underlying silicon nitride layer, without significant attack of the underlying silicon nitride layer.
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Tao Hun-Jan
Tsai Chia Shiung
Ackerman Stephen B.
Chaudhuri Olik
Mai Anh D.
Saile George O.
Taiwan Semiconductor Manufacturing Company , Ltd.
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