Process for producing a semiconductor device with a planar top s

Details Process for producing a semiconductor device with a planar top s Process for producing a semiconductor device with a planar top s

1997-07-07

1998-08-04

Quach, T. N.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438622, 438926, H01L 21283

Patent

active

057893136

ABSTRACT:
A method for fabricating a mask for forming a metallurgy system on a semiconductor device that provides a planar top surface is described. An initial mask pattern for the metallurgy system is designed that includes operative conductive lines that electrically connect device structure, and include parallel lines that are non-uniformly spaced, resulting in large areas. The mask design is re-designed to fill in parallel dummy lines in the large areas where the spacing of the conductive lines is equal to or greater than three times the feature size, or alternatively, the width of the lines.

REFERENCES:
patent: 4972580 (1990-11-01), Nakamura
patent: 5027188 (1991-06-01), Owada et al.
patent: 5032890 (1991-07-01), Ushiku et al.
patent: 5066997 (1991-11-01), Sakurai et al.
patent: 5077234 (1991-12-01), Scoopo et al.
patent: 5103282 (1992-04-01), Isomura et al.
patent: 5182235 (1993-01-01), Eguchi
"Improved Sub-Micron Inter-Metal Dielectric Gap-Filing Using TE08/Ozone APCVD", by E.J. Korczynski and A.H. Shih, Microelectronics Manufacturing Technology, Jan. 1992, pp. 22-27.

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