Method of making EEPROM cell device with polyspacer floating gat

Details Method of making EEPROM cell device with polyspacer floating gat Method of making EEPROM cell device with polyspacer floating gat

1996-10-24

1998-08-04

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438304, 438596, H01L 218247

Patent

active

057892970

ABSTRACT:
A novel electrically erasable programmable read only memory (EEPROM) cell for use in semiconductor memories includes a polyspacer floating gate. The EEPROM structure also includes a select gate covering a part of the channel of the EEPROM cell, with a polysilicon spacer adjacent to the select gate. The polysilicon spacer implements a floating gate that holds charge to program the EEPROM cell. In one embodiment, a isolation layer separates the select gate and the floating gate. The isolation layer and the floating gate extends over the remaining part of the channel. A second isolation layer is formed over select gate and the floating gate. A control gate is formed on the isolation layer. Between the drain and the control gate is the second isolation layer. A lightly doped drain (LDD) structure is formed at the drain adjacent.

REFERENCES:
patent: 4622737 (1986-11-01), Ravaglia
patent: 5284784 (1994-02-01), Manley
patent: 5478767 (1995-12-01), Hong
patent: 5550073 (1996-08-01), Hong

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