Method of making a semiconductor device having 4t sram and mixed

Details Method of making a semiconductor device having 4t sram and mixed Method of making a semiconductor device having 4t sram and mixed

1996-05-28

1999-02-02

Bowers, Jr., Charles L.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438238, 438233, 438210, 438200, H01L 218242

Patent

active

058664513

ABSTRACT:
An integrated process for forming a 4T SRAM and a mixed-mode capacitor, with logic, on the same integrated circuit, is provided. A semiconductor substrate is provided having field isolation regions, with a gate and gate oxide between the field isolation regions. Polysilicon interconnects are formed over a portion of the field isolation regions, only in a first memory region, and a bottom capacitor plate over a field oxide region in a capacitor region. Active regions are formed in the substrate, adjacent to each gate. Insulating spacers are formed on the sidewalls of the gates, polysilicon interconnects and the floating gate, and later removed from the interconnect. A layer of titanium silicide is formed over the gates and capacitor bottom plate, and also over the polysilicon interconnects and active regions. An interpoly oxide is formed over the semiconductor substrate. An opening is formed in the interpoly oxide over the polysilicon interconnect. A second layer of polysilicon is deposited over the substrate. The second layer of polysilicon is patterned to form a top capacitor plate, and to form a load resistor for the SRAM.

REFERENCES:
patent: 5066602 (1991-11-01), Takemoto et al.
patent: 5340762 (1994-08-01), Vora
patent: 5719079 (1998-01-01), Yoo et al.
S. Wolf, "Silicon Processing For The VLSI Era-vol. 2" Lattice Press, Sunset Beach, CA, p. 571-572.

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