Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-08-09
1998-08-18
Tsai, Jey
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438222, 438433, 438524, 438525, 438527, 148DIG85, 148DIG86, H01L 218238
Patent
active
057958017
ABSTRACT:
A trench is formed in a substrate, the trench defining an active region surface on the substrate, the trench having a trench sidewall. A trench insulation region is then formed in the trench. The substrate underlying the trench sidewall is doped with impurities, and after the first doping, the substrate underlying the active region surface is doped with impurities to form a well having an impurity concentration which increases towards the trench sidewall in a predetermined manner. To form the trench, an insulation layer preferably is formed on the substrate, a barrier layer is formed on the insulation layer, and the barrier layer and the insulation layer are patterned to form an insulation region on the substrate and a barrier region on the insulation region. The substrate is then etched using the barrier region and the insulation region as a mask to thereby form a trench in the substrate. Preferably, the first doping includes implanting ions into the substrate through the trench insulation region and the trench sidewall using the barrier region as a mask. The second doping preferably is preceded by removal of the barrier region, and includes implanting ions into the substrate through the active region surface. The first implantation preferably occurs at a predetermined angle of incidence oblique to the active region surface or, more preferably, over a predetermined range of angles of incidence. The first and second doping steps may include doping with impurities of the same conductivity type or with opposite conductivity types.
REFERENCES:
patent: 3901737 (1975-08-01), Dash
patent: 4415371 (1983-11-01), Soclof
patent: 4419150 (1983-12-01), Soclof
patent: 4466178 (1984-08-01), Soclof
patent: 4523369 (1985-06-01), Nagukubo
patent: 4533430 (1985-08-01), Bower
patent: 4534824 (1985-08-01), Chen
patent: 4653177 (1987-03-01), Lebowitz et al.
patent: 4756793 (1988-07-01), Peek
patent: 4918027 (1990-04-01), Fuse et al.
patent: 5047359 (1991-09-01), Nagatomo
patent: 5506168 (1996-04-01), Morita et al.
Tonti et al., Impact of Shallow Trench Isolation on Reliability of Buried-and Surface-Channel Sub-.mu.m PFET, IRPS, 1995, pp. 24-29.
Pham Long
Samsung Electronics Co,. Ltd.
Tsai Jey
LandOfFree
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