Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1997-10-30
2000-01-04
De Cady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714732, G06F 724
Patent
active
060121556
ABSTRACT:
A computerized method and system for automatically extracting an IEEE 1149.1 standard design from a netlist and performing compliance checking. The present invention receives the TAP (test access port) description and compliance enable ports of a netlist. The TAP controller is extracted and its state ports are identified, referenced in a boundary scan design database (BSDD) and its states are verified. The TAP controller is controlled so that the instruction register is located and referenced in the BSDD. The TAP controller is controlled so that the bypass register is found and the BSDD is updated. The TAP controller is controlled so that the shift and update cells of the boundary scan register (BSR) are found, the control, input and output BSR cells are characterized and the BSDD is updated. Primary input and output information is also inferred and the device.sub.-- ID register is found. Frontier pins are used to locate signatures of the remaining instructions and their test data registers are found. To infer the SAMPLE instruction, instructions selecting the BSR are groups and those that do not exhibit the behavior of the SAMPLE instruction are eliminated. Primary inputs and primary outputs are then inferred. The following instructions are then inferred: INTEST, HIGHZ, CLAMP, IDCODE and RUNBIST. As each of the above elements of the IEEE 1149.1 design are located, they are used to update the BSDD and are also inherently verified for compliance by the present invention. Intolerable violations flag a non-compliant design.
REFERENCES:
patent: 5497378 (1996-03-01), Amini et al.
patent: 5517637 (1996-05-01), Bruce, Jr. et al.
patent: 5572712 (1996-11-01), Jamal
patent: 5708773 (1998-01-01), Jeppesen, III et al.
patent: 5748497 (1998-05-01), Scott et al.
Edward B. Pitty, Denis Martin, Hi-Keung Tony Ma, "A Simulation-Based Protocol-Driven Scan Test Design Rule Checker," International Test Conference, pp. 999-1006, 1994.
Mascitelli, A. Affidavit of Alida Mascitelli and Attached Exhibits. Jun. 15, 1999.
Dahbura et al., "An Optimal Test Sequence for the JTAG/IEEE P1149.1 Test Access Port Controller", 1989 IEEE, pp. 55-61.
Beausang James
Singh Harbinder
Cady Albert De
Synopsys Inc.
Ton David
LandOfFree
Method and system for performing automatic extraction and compli does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for performing automatic extraction and compli, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for performing automatic extraction and compli will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1081211