Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-02-10
2008-03-25
Ellis, Kevin L. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
07350027
ABSTRACT:
A method and apparatus for hardware support of the thread level speculation for existing processor cores without having to change the existing processor core, processor core's interface, or existing caches on the L1, L2 or L3 level. Architecture support for thread speculative execution by adding a new cache level for storing speculative values and a dedicated bus for forwarding speculative values and control. The cache level is hierarchically positioned between the cache levels L1 and L2 cache levels.
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Gara Alan G.
Salapura Valentina
Ellis Kevin L.
International Business Machines - Corporation
Morris, Esq Daniel P.
Scully , Scott, Murphy & Presser, P.C.
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