4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Testing of error-check system

T. Scott Cummins

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Method and apparatus for detecting a bus deadlock in an...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate

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Method and apparatus for inserting an error signal onto a bidire

Error detection/correction and fault detection/recovery – Pulse or data error handling – Testing of error-check system
Patent

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Method for utilizing a single multiplex address bus between DRAM

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent

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Profile ID: LFUS-PAI-P-1705760

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