Method for utilizing a single multiplex address bus between DRAM

Details Method for utilizing a single multiplex address bus between DRAM Method for utilizing a single multiplex address bus between DRAM

1996-10-07

1999-05-04

Auve, Glenn A.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711 5, 395858, G06F 1300

Patent

active

059012986

ABSTRACT:
A memory interface device for interfacing between the local bus and a memory bus. The memory bus is coupled to a static memory and a dynamic memory. The interface device includes first and second internal buses coupled to a selecting device. The selecting device selectively couples one of the first and second internal buses to the memory bus. The memory interface device further includes an interface control unit having an input coupled to the local bus for receiving address and control signals. The interface control unit further has an output, coupled to the first internal bus for generating gating each data transfer in the burst in response to the address and control signals.

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