Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-09-14
2001-09-18
Ray, Gopal C. (Department: 2181)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C709S241000
Reexamination Certificate
active
06292910
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the field of validating the functionality of electronic systems, and more particularly to the field of validating the functionality of electronic systems by monitoring bus activity.
BACKGROUND OF THE INVENTION
In electronic systems that include busses for devices to communicate with each other, the occurrence of bus deadlocks decreases the robustness of the system. Therefore, an important part of validating the functionality of these systems is the detection of bus deadlocks or conditions that could lead to bus deadlocks.
A prior approach to detecting bus deadlocks is to set a timer to expire some time after a bus transaction is expected to be completed, then using the expiration of the timer as an indication that a deadlock has occurred. So as to prevent the timer from expiring when there is not a deadlock, the timer is set to accommodate any possible bus transaction, including those that have a duration much longer than that of a typical bus transaction. Then, however, when a deadlock occurs during a typical bus transaction, there can be a delay of many clock cycles before the timer expires. Sometimes, the number of clock cycles of delay can exceed the number of clock cycles for which the validation environment is able to store bus information for debug purposes, so the bus information related to the cause of the deadlock condition is purged by the time the timer expires. This situation can frustrate the validation and debug effort.
Therefore, a novel approach to detecting a bus deadlock in an electronic system has been developed.
SUMMARY OF THE INVENTION
An apparatus for detecting a bus deadlock is disclosed. The apparatus includes a bus tracker circuit to monitor bus transactions to detect a condition that indicates the occurrence of a wait cycle or a retry cycle. The apparatus also includes a counter circuit to indicate that the bus tracker circuit has detected the condition a predetermined number of times.
REFERENCES:
patent: 5067071 (1991-11-01), Schanin et al.
patent: 5682551 (1997-10-01), Pawlowski et al.
patent: 5889972 (1999-03-01), Allingham
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Ray Gopal C.
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