Clock generator having improved deskewer

Details Clock generator having improved deskewer Clock generator having improved deskewer

2008-02-07

2008-11-25

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S294000, C327S299000

Reexamination Certificate

active

07456674

ABSTRACT:
Disclosed is a clock generation circuit for generating a clock-out signal that has a fixed latency with respect to a clock-input signal. When multiple such clock generation circuits are utilized to feed clock signals to different digital logic circuits within an integrated circuit structure, differences in delay time, referred to as skew, are minimized. An embodiment of the clock generation circuit incorporates a waveform generator and a timing-improved deskewer. The waveform generator is clocked by a clock-in signal. The deskewer comprises a flip-flop, a level-sensitive latch, and a multiplexer. The flip-flop and latch are connected in parallel and each receives waveform signals from the waveform generator as well as the clock-in signal in order to generate output signals. The multiplexer gates the flip-flop and latch output signals with the clock-in signal in order to generate the clock-out signal. A testable deskewer for edge-sensitive multiplexer scan designs is also disclosed.

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