Architecture for implementing virtual multiqueue fifos

Details Architecture for implementing virtual multiqueue fifos Architecture for implementing virtual multiqueue fifos

2005-08-02

2005-08-02

Verbrugge, Kevin (Department: 2188)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S056000, C711S100000, C711S170000

Reexamination Certificate

active

06925506

ABSTRACT:
A circuit configured to provide a storage device comprising one or more virtual multiqueue FIFOs. The circuit is generally configured to operate at a preferred clock speed of a plurality of clock speeds.

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