FIFO memory system and method

Details FIFO memory system and method FIFO memory system and method

2005-09-20

2005-09-20

Kim, Hong (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S005000, C711S154000, C711S170000, C710S053000, C710S057000, C365S078000, C365S189030, C370S232000

Reexamination Certificate

active

06948030

ABSTRACT:
A FIFO memory system for multiple input channels, has a channel control logic coupled to a channel input signal. A pointer and flag logic block is coupled to an output of the channel control logic. A memory has an address bus coupled to the channel control logic and the pointer and flag logic.

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Cypress Semiconductor Corporation, CY7C43626 Data Sheet, Tri Bus FIFO, Oct. 6, 1998.

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