4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Digital logic testing

Singh Vinay Jitendra

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Method and apparatus for hardware co-simulation clocking

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Simulation of integrated circuitry within a high-level...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate

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Synchronization for a modeling system

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate

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Profile ID: LFUS-PAI-P-2992970

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