Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2009-05-19
2011-10-18
Garbowski, Leigh (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S121000, C717S104000, C717S109000, C712S225000
Reexamination Certificate
active
08042079
ABSTRACT:
Design synchronization for a High-Level Modeling System (“HLMS”) of an integrated circuit device (“IC”) is described. In a method for generating a netlist, a description of a first circuit block of a user design is input to a programmed computer system programmed with a computer-aided modeling system. The description includes output port information of the first circuit block and synchronization signal information. The computer-aided modeling system selects a circuit core for the first circuit block responsive to output port information and the synchronization signal information, the circuit core including port metadata. The computer-aided modeling system selects at least one macro responsive to the port metadata for generation of the netlist. The macro is for rate synchronized coupling of the first circuit block to a second circuit block of the user design. The computer-aided modeling system outputs the netlist including the macro.
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Dow Andrew
Jitendra Singh Vinay
Ma Haibing
Sundararajan Arvind
Garbowski Leigh
Maunu LeRoy D.
Thompson A. M.
Webostad W. Eric
Xilinx , Inc.
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