4. Static information storage and retrieval
  5. Read/write circuit
  6. Data refresh

Sam Dehganpour

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Address buffer circuit for a dram

Static information storage and retrieval – Read/write circuit – Data refresh
Patent

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Gate stress test of a MOS memory

Static information storage and retrieval – Read/write circuit – Testing
Patent

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High voltage circuit for use in programming memory circuits (EEP

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent

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Output buffer with improved di/dt

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent

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Profile ID: LFUS-PAI-P-649723

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