Output buffer with improved di/dt

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307246, 307296R, 307451, 307270, 307548, H03K 1704, H03K 1712, H03K 17284, H03K 17687

Patent

active

047587431

ABSTRACT:
An integrated circuit comprises a chip containing electric circuits in a package with leads. The chip receives power via the leads. The leads have inductance so that when there is a change in current flow (di/dt) through a lead there is a voltage which is developed between the end of the lead and the chip which can cause the chip to either malfunction or function poorly. The highest di/dt is generally caused by an output buffer that changes the logic state of its output. The typical output buffer has a pair of driver transistors that provide one of a logic high or logic low. The di/dt generated by these transistors is controlled by controlling the voltage on the gate of the transistor which is providing the particular logic state. This control reduces di/dt from that typically provided at the very beginning of a logic state transition but increases it over that typically provided immediately thereafter for the purpose of optimizing logic state transition speed for a given maximum di/dt.

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